Taiwan Semiconductor Manufacturing Comp. Ltd.

Coretronic Corporation

Chao-Chun Wang

Chung-Chi Ko

Po-Cheng Shih

Su-Jen Sung

Keith Kuang-Kuo Koai

Jen Hung Wang

Huan-Chieh Chen

Chih-Yu Wu

An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.

Methods for reducing dual damascene distortion

A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

Interconnect structure with dielectric cap layer and etch stop layer stack

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first capping layer on a dielectric structure over a substrate, and patterning the dielectric structure and the first capping layer to define cavities within the dielectric structure. A conductive material is formed within the cavities and a second capping layer is formed on the conductive material. An etch stop layer is formed along sidewalls and over an upper surface of the second capping layer. The etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer. The first thickness is greater than the second thickness.

Capping layer for improved deposition selectivity

The present disclosure provides a blocker plate, including a plate body having a plurality of through holes, a first zone from a center to a first radius of the plate body, having a first conductance, a second zone from the first radius to a second radius of the plate body, having a second conductance, a third zone from the second radius to a third radius of the plate body, having a third conductance, wherein the first radius is smaller than the second radius, the second radius is smaller than the third radius, and the second conductance is greater than the first conductance. A chemical vapor deposition (CVD) apparatus including the blocker plate is also disclosed.

Chemical vapor deposition apparatus and blocker plate

A projection system, a protection circuit and a current monitoring method of an image resolution enhancement device are provided. A light valve converts an illumination beam into an image beam. The image resolution enhancement device changes a transmission path of the image beam according to a driving current. The protection circuit detects the driving current. When the driving current is greater than or equal to a first current threshold, the protection circuit further compares the driving current with a second current threshold. When a duration time that the driving current is smaller than the second current threshold and greater than or equal to the first current threshold is greater than or equal to a time threshold, the protection circuit decreases the driving current to be smaller than the first current threshold to control the image resolution enhancement device. The projection lens converts the image beam into a projection beam.

Projection system, protection circuit and current monitoring method of image resolution enhancement device

The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for improved reliability. In some embodiments, the integrated chip has a dielectric layer disposed over a semiconductor substrate, and one or more metal layer structures disposed within the dielectric layer. A first capping layer is located over the dielectric layer at positions between the one or more metal layer structures, so that the first capping layer is located along an interface having the one or more metal layer structures interspersed between the first capping layer. A second capping layer is located over the one or more metal layer structures. An etch stop layer is arranged over the first capping layer and the second capping layer and laterally surrounds the second capping layer.

The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer.

Growing community of inventors

Hsinchu, Taiwan

Chao-Chun Wang