Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Chen Chen

Yi-Chen Huang

Wei-Kay Chiu

Tze-Liang Lee

Li-Chih Chao

A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of dielectric insulating layers revealing a first etching resistant layer overlying a conductive area; a plurality of dielectric insulating layers sequentially stacked to have alternating etching rates to a preferential etching process; subjecting the anisotropically etched opening to the preferential etching process whereby the sidewalls of the anisotropically etched opening are preferentially etched to produce etched dielectric insulating layers to form roughened sidewall surfaces; anisotropically etching through the etching resistant layer to reveal the conductive area; and, filling the anisotropically etched opening with a metal to form a metal filled semiconductor feature.

Metal filled semiconductor features with improved structural stability

A new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which is provided top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug. A second layer of passivation material is deposited, the second layer of passivation is patterned and etched exposing the surface of the first layer of passivation overlying the fuse metal and exposing the surface of the stack of hard mask layers overlying the created metal plug. The stack of hard mask layers is then removed from the surface of the metal plug, exposing the surface of the metal plug to serve as a contact pad and further reducing the thickness of the first layer of passivation over the surface of the fuse metal, making the fuse more accessible for fuse blowing.

Integrated process for fuse opening and passivation process for CU/LOW-K IMD

A new method is provided for the creation of an opening over which the second electrode of a MIM capacitor is to be deposited. The first electrode of the MIM is created in a first layer of Fluorine doped Silicon dioxide (SiO ) Glass (FSG) . A layer of insulation comprising silicon nitride is deposited over the surface of the first electrode. A second layer of Fluorine doped Silicon dioxide (SiO ) Glass (FSG) is deposited over the surface of the layer of silicon nitride, an etch stop layer of silicon nitride is deposited over the surface of the second layer of FSG. The layers of etch stop and the second layer of FSG are patterned and etched using a dry etch, stopping on the layer-of insulation and exposing the surface of the layer of insulation. Next-and of critical importance to the invention is a step of photoresist ashing and oxidation of the surface of the layer of silicon nitride. The layer of photoresist can now be removed while concurrently, using a wet strip, the layer of silicon nitride oxidation is removed from the surface of the layer of silicon nitride. The process of creating a MIM capacitor can then proceed by creating the second electrode of the MIM capacitor.

CU second electrode process with in situ ashing and oxidation process

A method and apparatus for curing a photoresist that is deposited in liquid form and spun on a surface of a wafer leaving a thin film to be cured. This invention teaches methods for curing the resist with improved thickness control using front side heating.

Growing community of inventors

Matou, Taiwan

Chao-Chen Chen