Sandisk Technologies Inc.

Silicon Storage Technology, Inc.

Western Digital Technologies, Inc.

Sandisk Corporation

Changyuan Chen

Biswajit Ray

Mohan Dunga

Dana Lee

Ya-Fen Lin

Yuniarto Widjaja

John W Cooksey

Feng Gao

Yingda Dong

Jeffrey W Lutze

Gerrit Jan Hemink

Hua-Ling Cynthia Hsu

Cynthia Hsu

Ching-Huang Lu

Chris Avila

Gautam Ashok Dusija

Anubhav Khandelwal

Deepak Raghu

Guirong Liang

Farookh Moogat

Vinh Diep

Himanshu Hemant Naik

Abuzer Azo Dogan

Eran Sharon

Idan Alrod

Masaaki Higashitani

Deepanshu Dutta

Nian Niles Yang

Peter Rabkin

Jianmin Huang

Man Lung Mui

Bomy A Chen

Henry Chin

Ting Luo

Seungpil Lee

Mark Murin

Grishma Shah

Hao Nguyen

Jack Frayer

Jeng-Wei Yang

Ishai Ilani

Philip David Reusswig

Jongmin Park

William Saiki

Chun-Ming Chen

David Rozman

Alon Eyal

Joanna Lai

Han-Ping Chen

Yee Lih Koh

Chris Yip

Bijesh Rajamohanan

Felix (Ying-Kit) Tsui

Ching Huang Lu

Wei-Cheng Lien

Vamsi Krishna Sakhamuri

Gianfranco Pellegrini

Xiuhong Chen

Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.

Programming to minimize cross-temperature threshold voltage widening

A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Post write erase conditioning

Techniques are described for reducing program disturb including neighbor word interference in a memory device. Voltages applied to the word lines adjacent to the selected word line WLn during program and read operations are adjusted. The adjacent word lines include WLn&#x2212;1, a source-side adjacent word line of WLn, and WLn+1, a drain side adjacent word line of WLn. In one aspect, VWLn&#x2212;1&#x3c;VWLn+1 during the verify tests of the program operation for the data states above the lowest programmed data state and VWLn&#x2212;1=VWLn+1 during the verify test for the lowest programmed data state. Also, VWLn&#x2212;1&#x3c;VWLn+1 during a read operation which distinguishes between the programmed data states and VWLn&#x2212;1=VWLn+1 during a read operation which distinguishes between erased state and the lowest programmed data state.

Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line

Systems, methods, and devices of the various embodiments provide both 'string-sharing' drain select gate electrodes and 'string-selective' drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.

Three dimensional NAND memory device with drain select gate electrode shared between multiple strings

Systems and methods for string-based erase verify to create partial good blocks are disclosed. A block in non-volatile flash memory may include multiple strings. In practice, one string may be slower to erase than other strings. In analyzing the strings, the memory device may iteratively analyze the strings to verify as erased. As one example, the iterations are modified by changing which strings are erased in the subsequent iterations (e.g., only the strings that fail the erase verify). As another example, a predetermined number of iterations are performed after a majority of the strings are verified as erased. In this way, the strings verified as erased need not undergo more deep erasing, which may damage the strings. Further, if fewer than all of the strings are verified as erased, the memory device may designate the block as a partially good block.

System and method for string-based erase verify to create partial good blocks

Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.

Erase speed based word line control

A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.

Memory write verification using temperature compensation

Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.

Non-volatile memory with methods to reduce creep-up field between dummy control gate and select gate

An erase operation includes one or more erase depth checks to detect the occurrence of shallow erased memory cells at the end of an erase process. Memory cells are subjected to erase and erase verification until erase verification success is achieved. At the end of successful erase verification, a subset of memory cells is read to detect an erase depth or level of the memory cells. If the erase depth check indicates that the subset memory cells are in a shallow erased condition, additional erasing and verification is performed.

Erase for partially programmed blocks in non-volatile memory

Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

Cell current based bit line voltage

In solid-state memory, such as flash memory, a section of memory is typically erased prior to each time data is programmed therein. In contrast, systems and methods for programming a solid-state memory device with writes from different data sets without an intervening erase are disclosed. For example, the memory device may first erase a block and thereafter program the block with a first data set, with some cells in an erased state and other cells in a non-erased state. After programming the first data set into the block and without erasing the block, the memory device programs the block with a second data set that is at least partially different from the first data set. In this regard, some of the cells, which were in a non-erased state after programming with the first data set, are in an erased state after programming with the second data set.

System and method for programming a memory device with multiple writes without an intervening erase

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

Method of programming a continuous-channel flash memory device

Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

System solution for first read issue using time dependent read voltages

Growing community of inventors

San Ramon, CA, United States of America

Changyuan Chen