Intel Corporation

Changyok Park

Andy Chih-Hung Wei

Guillaume Bouche

Charles Henry Wallace

Mohit K Haran

Hyuk Ju Ryu

Disclosed herein are IC structures with decoupling capacitors based on dummy TSV plates provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example decoupling capacitor includes first and second capacitor plates and a capacitor insulator between them. Each capacitor plate is a different blind, plate-like opening in the support structure, the openings at least partially filled with one or more conductive materials. The capacitor plate openings are referred to herein as 'dummy TSV plates' because they may be fabricated while providing regular TSV openings in the support structure. Such decoupling capacitors may be better suited for high-speed microprocessor applications than conventional off-chip decoupling capacitors and may advantageously allow integrating on-chip decoupling capacitors with an ample amount of capacitive decoupling, limited or no additional processing steps on top of regular TSV processing, and in areas that may not have been used otherwise.

Decoupling capacitors based on dummy through-silicon-via plates

A capacitor includes a first die with a first side and a second side, wherein the first side of the first die includes a trace pattern. The capacitor also includes and a second die with a first side and a second side, wherein the first side of the second die includes the trace pattern. The first side of the first die and the first side of the second die are coupled to form a trace pattern of the capacitor, wherein the trace pattern of the capacitor comprises an interdigitated pattern, a first pad, and a second pad at an interface of the first side of the first die and the first side of the second die, the first pad at a first side of the interdigitated pattern, and the second pad at a second side of the interdigitated pattern, the second side laterally opposite the first side.

Capacitor formed with coupled dies

Disclosed herein are transistor arrangements with trench contacts that have two parts—a first trench contact and a second trench contact—stacked over one another. Such transistor arrangements may be fabricated by forming a first trench contact over a source or drain contact of a transistor, recessing the first trench contact, forming the second trench contact over the first trench contact, and, finally, forming a gate contact that is electrically isolated from, while being self-aligned to, the second trench contact. Such a fabrication process may provide improvements in terms of increased edge placement error margin, cost-efficiency, and device performance, compared to conventional approaches to forming trench and gate contacts. The conductive material of the first trench contact may also be deposited over the gate electrodes of transistors, forming a gate strap, to advantageously reduce gate resistance.

Transistor arrangements with stacked trench contacts and gate straps

Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.

Buried power rails with self-aligned vias to trench contacts

Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.

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Portland, OR, United States of America

Changyok Park