Texas Instruments Corporation

Changming Jin

Jiong-Ping Lu

Joseph D Luttmer

Sameer Kumar Ajmera

Patricia Beauregard Smith

Wei-Yung Hsu

Guoqiang Xing

Tae S Kim

Richard Scott List

Wei William Lee

Phillip D Matz

Qing-Tang Jiang

Ju-Ai Ruan

David Permana

Qi-Zhong Hong

Kelly Jay Taylor

Somnath S Nag

Ting Yiu Tsui

Noel M Russell

Tz-Cheng Chiu

Trace Quentin Hurd

Sopa Chevacharoenkul

Andrew McKerrow

Kenneth Joseph Newton

Stacey A Yamanaka

Heungsoo Park

Anand J Reddy

Satyavolu Papa Rao

R Scott List

Andrew J Mckerrow

A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

N2 based plasma treatment for enhanced sidewall smoothing and pore sealing of porous low-k dielectric films

A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

Semiconductor device manufactured by reducing hillock formation in metal interconnects

One aspect of the invention provides a method of forming a semiconductor device (). One aspect includes forming transistors () on a semiconductor substrate (), forming a first interlevel dielectric layer () over the transistors (), and forming metal interconnects () within the first interlevel dielectric layer (). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer () over the metal interconnects () and the first interlevel dielectric layer () within a deposition tool. An adhesion layer () is formed on the SiCN layer (), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer () is formed over the adhesion layer ().

Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer

[object Object]

A method of manufacturing a semiconductor device includes the steps of providing a semiconductor substrate (), forming a dielectric layer () over the semiconductor substrate (), and etching a trench or a via () in the dielectric layer () to expose a portion of the surface of the semiconductor substrate (). The method also includes the step of forming a conductive layer () within in the trench or the via (). The method further includes the steps of polishing a portion of the conductive layer () and annealing the conductive layer () at a predetermined temperature. Moreover, the conductive layer () also includes a dopant, and the dopant diffuses substantially to the surface of the top side of the conductive layer () to form a dopant oxide layer () when the conductive layer () is annealed at the predetermined temperature and the dopant is exposed to oxygen.

Semiconductor device with a conductive layer including a copper layer with a dopant

A trench and via structure is formed in a low k dielectric layer () formed over a silicon substrate (). Super critical COand a first silylization agent are used to form a chemically bonded high density surface layer (). Silanol species are removed from the low k dielectric layer () using super critical COand a second silylization agent. A barrier layer () and copper () are used to fill the trench and via structure.

Method to reduce silanol and improve barrier properties in low k dielectric ic interconnects

Semiconductor devices and methods of manufacturing such semiconductor devices

Disclosed is a system for fabricating a semiconductor device (). An interconnect structure () is formed on the semiconductor device () and a cap () is deposited over the interconnect structure (). The interconnect structure () is annealed with the overlying cap () in place. The cap () is then removed after the interconnect structure () is annealed.

System for improving thermal stability of copper damascene structure

A method of forming an integrated circuit including an organosilicate low dielectric constant insulating layer () formed of a substitution group depleted silicon oxide, such as an organosilicate glass, is disclosed. Subsequent plasma processing has been observed to break bonds in such an insulating layer (), resulting in molecules at the surface of the film with dangling bonds. Eventually, the damaged insulating layer () includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer () to a thermally or plasma activated fluorine, hydrogen, or nitrogen, which reacts with the damaged molecules to form a passivated surface for the insulating layer ().

Chemical treatment of low-k dielectric films

A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer ( ) which invades open surface pores ( ) of xerogel ( ).

Integrated circuit dielectric and method

Porous integrated circuit dielectric with decreased surface porosity

A xerogel aging system includes an aging chamber ( ) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.

According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.

Methods for forming multiple damascene layers

A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer ( ) is formed over the dielectric layer ( ). A sacrificial layer ( ) is formed over the SiC layer ( ). A trench ( ) is etched in the sacrificial layer ( ), the SiC layer ( ) and the dielectric layer ( ). A sputter etch of the sacrificial layer ( ) is used to create a wider opening at a top of the sacrificial layer ( ) than at a top of the dielectric layer ( ). A barrier layer ( ) and copper seed layer ( ) are formed. The trench ( ) is then filled with copper ( ). CMP is used to remove the excess copper ( ) and barrier layer ( ) stopping on the SiC ( ).

Use of a sacrificial layer to facilitate metallization for small features

A carbon hardmask ( ) for etching hard-to-etch materials ( ) such as Pt, Ir, Ru, IrO , RuO , BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sputter etching using argon and limited or no oxygen may be used to etch the hard-to-etch materials ( ) with high selectivity to the carbon hardmask ( ).

Growing community of inventors

Plano, TX, United States of America

Changming Jin