Micron Technology Incorporated

Intel Corporation

Changhyun Lee

Akira Goda

Haitao Liu

William C Filipiak

One embodiment of a memory device includes an array of multiple-level memory cells and a controller. The controller is configured to program the multiple-level memory cells via a multiple-pass programming operation, the multiple-pass programming operation to program lower page data in a first pass and program higher page data in a second pass such that memory cells to be programmed to a higher level are programmed in parallel with memory cells to be programmed to a lower level.

Programming memory cells at two different levels in parallel

Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

Memory device including multiple select gates and different bias conditions

One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes programming higher page data to the memory cells in a second pass of the multiple-pass programming operation such that higher page data subject to the programmed lower page data is programmed prior to higher page data subject to erase data.

Programming memory cells where higher levels are programmed prior to lower levels

One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes reprogramming the lower page data to the memory cells prior to programming higher page data to the memory cells in a second pass of the multiple-pass programming operation.

Programming multiple-level memory cells with multiple-pass

Technology for a memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can apply a first voltage level to a selected wordline associated with the plurality of memory cells during a body reset operation. The memory controller can apply a second voltage level to an unselected wordline associated with the plurality of memory cells during the body reset operation. The selected wordline can transit to a stable negative pillar potential, such that selected memory cells associated with the selected wordline can have a reduced threshold voltage instability.

Selective body reset operation for three dimensional (3D) NAND memory

Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. Recesses extend into the conductive levels. The conductive levels have projections above and below the recesses. The projections have outer edges. An outer periphery of an individual conductive level is defined by a straight-line boundary extending from the outer edge of the projection above the recess in the individual conductive level to the outer edge of the projection below the recess in the individual conductive level. A depth of the recess is defined as a horizontal distance from the straight-line boundary to an innermost periphery of the recess. The recesses have depths of at least about 5 nm. Charge-blocking regions extend within the recesses. Charge-storage structures are along the charge-blocking regions. Gate dielectric material is along the charge-storage structures. Channel material is along the gate dielectric material.

Integrated structures

Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material.

Growing community of inventors

Boise, ID, United States of America

Changhyun Lee