Intel Corporation

Changhua Liu

Leonel R Arana

Aleksandar Aleksov

Robert Alan May

Kristof Darmawikarta

Steve S Cho

Xiaoying Guo

Srinivas V Pietambaram

Sri Ranga Sai Boyapati

Pooya Tadayon

Gang Duan

Liang Zhang

Zhichao Zhang

Jeremy D Ecton

Hiroki Tanaka

Benjamin Duong

Haobo Chen

Chung Kwang Tan

Rahul N Manepalli

Brandon C Marin

Yonggang Li

Tarek A Ibrahim

Suddhasattwa Nad

Bai Nie

Dingying David Xu

Srikant Nekkanty

Nicholas S Haehn

Deepak Goyal

Amram Eitan

Jung Kyu Han

Zhiyong Wang

Oscar Ojeda

Hongxia Feng

Srinivas Venkata Ramanuja Pietambaram

Hari Mahalingam

Arnab Roy

Kevin T McCarthy

Jianyong Mo

Nilanjan Z Ghosh

Vahidreza Parichehreh

Timothy White

Keith J Martin

Kyle Mcelhinny

Allan Ketelsen

Whitney Bryks

A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

First layer interconnect first on carrier approach for EMIB patch

Position controlled waveguides and methods of manufacturing the same are disclosed. An example apparatus includes a substrate with a channel that extends into a first surface of the substrate to a second surface of the substrate, wherein the second surface is recessed relative to the first surface; buffer material having a first index of refraction on the second surface of the substrate; and a waveguide on the buffer material, the waveguide having a second index of refraction that is higher than the first index of refraction.

Position controlled waveguides and methods of manufacturing the same

Various embodiments disclosed relate to photonic assemblies. The present disclosure includes methods for packaging a photonic assembly, including attaching a bridge die to a glass substrate, attaching an electronic integrated circuit die to the glass substrate and the bridge die, attaching a photonic integrated circuit die to the glass substrate and the bridge die, bonding a coupling adapter to the glass substrate and in situ forming a waveguide in the coupling adapted, the waveguide aligning with the photonic integrated circuit die.

Die last and waveguide last architecture for silicon photonic packaging

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates

Techniques and mechanisms for facilitating horizontal communication with a photonic integrated circuit (PIC) chip, and a lens structure which is optically coupled thereto. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective first divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A lens structure, which is adjacent to the IECs, comprises a second divergent lens surface having an orientation which is substantially orthogonal to the respective orientations of the first divergent lens surfaces. In another embodiment, an edge of the PIC chip forms one or more recess structures, and the lens structure comprises one or more tenon portions which each extends into a respective recess structure of the one or more recess structures.

Device, method and system for optical communication with a photonic integrated circuit chip and a transverse oriented lens structure

Techniques and mechanisms for optically coupling a photonic integrated circuit (PIC) chip to an optical fiber via a planar optical waveguide structure. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A planar optical waveguide structure, which is adjacent to the IECs, comprises a core which is optically coupled between the PIC chip and an array of optical fibers. In another embodiment, an edge of the PIC forms a stepped structure, wherein an upper portion of the stepped structure comprises the plurality of coplanar IECs, and a lower portion of the stepped structure extends past the plurality of coplanar IECs.

Device, method and system for optical communication with a waveguide structure and an integrated optical coupler of a photonic integrated circuit chip

Apparatuses, systems and methods associated with package substrate design with variable height conductive elements within a single layer are disclosed herein. In embodiments, a substrate may include a first layer, wherein a trench is located in the first layer, and a second layer located on a surface of the first layer. The substrate may further include a first conductive element located in a first portion of the second layer adjacent to the trench, wherein the first conductive element extends to fill the trench, and a second conductive element located in a second portion of the second layer, wherein the second conductive element is located on the surface of the first layer. Other embodiments may be described and/or claimed.

Substrate with variable height conductive and dielectric elements

Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.

Method to achieve tilted patterning with a through resist thickness using projection optics

Embodiments disclosed herein include a lithographic patterning system and methods of using such a system to form a microelectronic device. In an embodiment, the lithographic patterning system includes an actinic radiation source, a stage where a major surface of the stage is for supporting a substrate with a resist layer, and a first prism over the stage, where the first prism comprises a first face that is substantially parallel to the major surface of the stage. In an embodiment, the lithographic patterning system further comprises a second prism, where the second prism comprises a first surface that is substantially parallel to a second surface of the first prism, and where a second surface of the second prism has a reflective coating.

Method to achieve tilted patterning with a through resist thickness

Embodiments disclosed herein include a lithographic patterning system and methods of using such a system to form a microelectronic device. The lithographic patterning system includes an actinic radiation source, a stage having a surface for supporting a substrate with a resist layer, and a prism with a first surface over the stage, where the first surface has a masked layer and is substantially parallel to the surface of the stage. The prism may have a second surface that is substantially parallel to the first surface. The first and second surfaces are flat surfaces. The prism is a monolithic prism-mask, where an optical path passes through the system and exits the first surface of the prism through the mask layer. The system may include a layer disposed between the mask and resist layers. The mask layer of the prism may pattern the resist layer without an isolated mask layer.

Prism-mask for angled patterning applications

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

Dual-damascene zero-misalignment-via process for semiconductor packaging

The systems and methods described herein use at least one etchant and at least one photochemically active material in conjunction with electromagnetic energy applied simultaneous with the etchant and photochemically active material during the etching process. The interaction between the electromagnetic energy and the photochemically active material preferentially increases the etch rate in a direction along the axis of incidence of the electromagnetic energy, thereby permitting the anisotropic formation of voids within the semiconductor substrate. These anisotropic voids may be more closely spaced (i.e., arranged on a tighter pitch) than the isotropic voids produced using conventional etching technologies. By placing the voids in the semiconductor substrate on a tighter pitch, greater component density may be achieved.

Anisotropic etching systems and methods using a photochemically enhanced etchant

Growing community of inventors

Chandler, AZ, United States of America

Changhua Liu