Texas Instruments Corporation

ChangFeng F Xia

Jiong-Ping Lu

Linlin Chen

Ricky A Jackson

Arunthathi Sivasothy

Asad Mahmood Haider

Trace Quentin Hurd

Asad M Hauder

A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.

Vapor deposition system using benzotriazole (BTA) and isopropyl alcohol for protecting copper interconnects

A method for cleaning a semiconductor device has the steps of securing a wafer () with a modified chuck () and applying a cleaning solution () to the backside () of the wafer (). The cleaning solution () is formulated to remove PTFE from the wafer (). The cleaning solution () is applied to the edge () of the wafer () because of the characteristics of the modified chuck () to remove PTFE impurities that gather on the edge () of the wafer ().

Method and apparatus for removing polymer residue from semiconductor wafer edge and back side

An improved copper ECD process. After the copper seed layer () is formed, a first portion of copper film () is plated onto the surface of the seed layer (). The surface of the first portion of the copper film () is then rinsed to equalize the organic adsorption on all sites to prevent preferential copper growth in dense areas. After rinsing, the remaining copper of the copper film () is electrochemically deposited.

Plating-rinse-plating process for fabricating copper interconnects

The present invention provides a system () for remediating aberrations along the perimeter of a semiconductor wafer (). The system includes a cleaning apparatus () within which the wafer is spun within a confined area. A chuck () defines the confined area, having a sidewall that extends above the upper surface () of the wafer and surrounds the perimeter of the wafer. The chuck also has a bottom wall, with an aperture formed therein, beneath the wafer. The system includes an isolation barrier (), disposed atop the bottom wall of the chuck and around the aperture, in proximity to the lower surface so of the wafer. This forms a narrow gap () between the barrier and the wafer. A pressurized source forcefully directs a gas () at and along the lower surface of the wafer. The system also includes a remediation solution () that is applied to the upper surface of the wafer. The solution is forced into a well () formed between the chuck sidewall and the perimeter of the wafer, such that the solution bathes the perimeter of the wafer.

Versatile system for wafer edge remediation

Vapor deposition of benzotriazole (BTA) for protecting copper interconnects

A cleaning chemistry for lowering defect levels on the backside of a semiconductor wafer after chemical mechanical planarization (CMP). In a preferred embodiment of the present invention, a cleaning chemistry comprising nitric acid, hydrofluoric acid, and phosphoric acid in solution with deionized water is applied to the wafer surface to be cleaned preferably while subjected to megasonic assist cleaning. The wafer is preferably then subjected to brush scrubbing and a deionized water rinse with megasonic assist cleaning.

Modified clean chemistry and megasonic nozzle for removing backside CMP slurries

An embodiment of the invention is a method to reduce the corrosion of copper interconnects by forming a thiol ligand coating on the surface of the copper interconnects

Copper surface passivation during semiconductor manufacturing

The present invention provides, in one embodiment, a method of forming a metal layer over a semiconductor wafer. The method includes the chemical reduction of copper oxide ( ) over the deposited copper seed layer ( ) by exposure to a substantially copper-free reducing agent solution ( ), such that the copper oxide ( ) is substantially converted to elemental copper, followed by electrochemical deposition of a second copper layer ( ) over the copper seed layer ( ). Such methods and resulting conductive structures thereof may be advantageously used in methods to make integrated circuits comprising interconnection metal lines.

Growing community of inventors

Plano, TX, United States of America

ChangFeng F Xia