Micron Technology Incorporated

Intel Corporation

Intel Ndtm US LLC

Sk Hynix Nand Product Solutions Corp.

Chang Wan Ha

Deepak Thimmegowda

Graham Richard Wolstenholme

Qiang Tang

Ali Khakifirooz

Pranav Kalavade

Hang Tian

Jong Kang

Aaron S Yip

Ebrahim Abedifard

Richard M Fastow

Ramin Ghodsi

Ravi H Motwani

Xiaojiang Guo

Chuan Lin

Violante Moschiano

Tommaso Vali

Zengtao T Liu

Shankar Natarajan

Uday Chandrasekhar

Khaled Hasnat

Shafqat Ahmed

Sagar Upadhyay

Mattia Cichocki

Trupti Bemalkhedkar

Binh N Ngo

Liu Liu

Binh Ngo

Ahsanur Rahman

David Meyaard

Soo-yong Park

Richard M Gularte

Guido Luciano Rizzo

Chee Law

Hoon Koh

Radhika Chinnammagari

An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

Split block array for 3D NAND memory

Systems, apparatuses, and methods may provide for technology that groups a plurality of wordline drivers together and supports these grouped wordline drivers via a shared multiplexer, a shared level shifter, and/or one or more shared multi-well level shifters. In one example, such technology includes a shared multiplexer and a first and second grouped global wordline driver coupled to the shared multiplexer. The shared multiplexer is to access data state information from a plurality of memory cells. The first grouped global wordline driver is to output a first plurality of wordlines associated with a first plane. The second grouped global wordline driver is to output a second plurality of wordlines associated with a second plane, where the second plane is different than the first plane.

Grouped global wordline driver with shared bias scheme

Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.

Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device

The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.

Asymmetric junctions of high voltage transistor in NAND flash memory

A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

Reducing power consumption in nonvolatile memory due to standby leakage current

Examples herein relate to determining a number of defective bit lines in a memory region prior to applying a program or erase voltages. If a threshold number of bit lines that pass during a program or erase verify operation is used to determine if the program or erase operation passes or fails, the determined number of defective bit lines can be used to adjust the determined number of passes or fails. In some cases, examples described herein can avoid use of extra bit lines and look-up table circuitry to use in place of defective bit lines and save silicon space and cost associated with the use of extra bit-lines. In some examples, a starting magnitude of a program voltage signal can be determined by considering a number of defective bit lines.

Defective bit line management in connection with a memory access

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Devices including stair step structures, and related apparatuses and memory devices

An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.

Program verification time reduction in non-volatile memory devices

Memory devices and related methods

Methods of operating a memory device include comparing an input address to one or more addresses stored in the memory device and indicative of problematic memory cells of the memory device, determining a status value of an indicator corresponding to a matched address if the input address matches a stored address, and storing data corresponding to the input address to a first memory array of the memory device and to a second memory array of the memory device if the indicator has a first status value. Methods may further include storing the data corresponding to the input address to only the first memory array or the second memory array if the indicator has a second status value.

Methods of operating a memory device

Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.

Power management

Methods of operating integrated circuit devices include generating a voltage level at a particular node in response to a first voltage level applied to a termination device and a second voltage level applied to a reference resistance; determining whether a plurality of available resistance values of the termination device satisfy a criterion that each available resistance value is either less than a resistance value of the reference resistance, or each available resistance value is greater than the resistance value of the reference resistance; and, when the plurality of available resistance values of the termination device satisfy the criterion, determining whether a voltage level generated at the particular node for a particular available resistance value of the plurality of available resistance values is between a voltage level of a first reference voltage and a voltage level of a second reference voltage.

Testing impedance adjustment

Stair step formation using at least two masks

Methods of operating integrated circuit devices are useful in testing impedance adjustment. Methods include connecting a node of the integrated circuit device to a first voltage node through a reference resistance and connecting the node to a second voltage node through a termination device, and comparing a voltage level at the node to a reference voltage for at least one resistance value of the termination device. When no available resistance value of the termination device generates a voltage level at the node that is deemed to match the reference voltage, the voltage level of the reference voltage may be altered, and the voltage level at the node may be compared to the altered reference voltage. When the voltage level at the node is deemed to match the altered reference voltage, the termination device may be deemed as passed. Otherwise, the termination device may be deemed as failed.

Growing community of inventors

San Ramon, CA, United States of America

Chang Wan Ha