Macronix International Co., Ltd.

Chang-Ting Chen

Kuen-Long Chang

Ken-Hui Chen

Chun-Hsiung Hung

Chin-Hung Chang

Nai-Ping Kuo

Chung-Kuang Chen

Shang-Chi Yang

Chun-Jen Huang

Chi-Ming Chen

Wen-Chieh Lee

Kuan-Ming Lu

A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.

Devices and operation methods for configuring data strobe signal in memory device

A configurable clock circuit on an integrated circuit, such as an integrated circuit memory, can be configured to utilize external multiple phase clocks and external single phase clocks to produce an internal clock signal in a form compatible with the integrated circuit.

Configurable clock interface device

A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.

Non-volatile memory device and method for shortened erase operation during testing

Method and apparatus for shortened erase operation

A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.

Dynamic driver circuit

A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Scheme of semiconductor memory and method for operating same

A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the ntransistor are respectively transformed into a source voltage and a drain voltage in an nreading period, and the voltage level of the second terminal of the (n+1)transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mtransistor are respectively transformed into the source voltage and the drain voltage in an mreading period. The source voltage equals the ground voltage.

Sequential memory and accessing method thereof

Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Method and apparatus for implementing high speed memory

A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

Memory device with rapid word line switch

A semiconductor memory with shielding effect is disclosed in the invention. The memory includes at least a plurality of word lines, one ground line control unit, and a plurality of memory units. Every memory unit includes a primary bit line, a ground line, a first equivalent switch, and a second equivalent switch. The primary bit line is enabled by a control signal. The ground line and the ground line control unit are electrically connected. The first equivalent switch is coupled to both the primary bit line and the ground line, and is controlled by the control signal of the previous memory unit. The second equivalent switch is coupled to both the primary bit line and the ground line of the next memory unit, and is controlled by the control signal of the next memory unit.

Growing community of inventors

Hsinchu, Taiwan

Chang-Ting Chen