Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Chang-Sub Lee

Dong-Gun Park

Jeong-Dong Choe

Shin-Ae Lee

Seong-Ho Kim

Sung-min Kim

Sung-Min Kim

Dong-yean Oh

Ji-Young Kim

Jung-Woo Kim

Ki-Chul Park

Jai-Hyuk Song

Won-sang Song

Sam-Young Kim

Young-Jin Wee

Chang-Hyun Lee

Chang-Woo Oh

Woon-Kyung Lee

Hyun-Jae Kim

Sung-young Lee

Keun-Ho Lee

Dong-Hyun Kim

Dong-Ho Lee

Young-Ho Lim

Ki-Tae Park

Jung-Hwan Kim

Jung-Hoon Park

Eun-jung Yun

Sung-soo Lee

Jeong-Hyuk Choi

Jong-Hwan Park

Sang-jun Park

Du-Heon Song

Yoon-Seop Eom

Chang-Seok Rho

Hyo-June Kim

Seong-ho Kim

Jae-Choel Paik

Won-Mo Park

Chong-In Chung

Kee-Hyun Paik

Jeong-Ho Lyu

Tae-Il Yoon

Jeong-Dong Choi

Jai Hyuk Song

An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL&#x3c;i&#x3e;, a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Chfrom a second local channel Ch. As the location i of the selected wordline WL&#x3c;i&#x3e; increases close to the SST, the second channel potential Vchtends to increase excessively, causing errors. The excessive increase of Vchis prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL&#x3c;i+1 through WL&#x3c;n&#x2192;), only if the selected wordline WL&#x3c;i&#x3e; location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.

NAND flash memory device and method of operating same to reduce a difference between channel potentials therein

A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.

Methods of fabricating non-volatile memory devices including double diffused junction regions

Non-volatile memory devices including double diffused junction regions

Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

Metal oxide semiconductor field effect transistors (MOSFETs) including recessed channel regions and methods of fabricating the same

A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Methods of fabricating semiconductor devices with enlarged recessed gate electrodes

A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.

Nonvolatile semiconductor memories for preventing read disturbance and reading methods thereof

In an embodiment, an image sensor includes an isolation layer disposed in a semiconductor substrate to define a first active region and a second active region extending from the first active region. A photodiode is disposed in a portion of the first active region. A floating diffusion region is provided in the second active region at a position spaced apart from the photodiode. A transfer gate electrode is disposed on the second active region between the photodiode and the floating diffusion region. The transfer gate electrode is disposed to cover both sidewalls and an upper portion of the second active region. The transfer gate electrode has a region extending onto the first active region and overlapping the photodiode. The photodiode has a protrusion into the second active region at the portion adjacent to the transfer gate electrode. A deep n-impurity region of the photodiode extends in the protrusion.

Image sensor having 3-dimensional transfer transistor and its method of manufacture

Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Methods of fabricating field effect transistors having multiple stacked channels

Semiconductor devices with enlarged recessed gate electrodes

MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

MOS Transistors having inverted T-shaped gate electrodes and fabrication methods thereof

A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

Semiconductor memory devices and methods for forming the same

A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portion includes a desired shape.

Methods for fabricating transistors having trench gates

A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Self-aligned semiconductor contact structures

In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to a sidewall of the trench, respectively. A gate electrode filling the trench is formed. Source/drain regions are formed at portions of the substrate adjacent to the sidewall of the gate electrode. Stopper regions are formed at portions of the substrate beneath the source/drain regions and beneath the first and second threshold voltage control regions, respectively. The buried channel type transistor has a high breakdown voltage between the source/drain regions although a threshold voltage thereof is low.

Buried channel type transistor having a trench gate and method of manufacturing the same

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Gyeonggi-do, South Korea

Chang-Sub Lee