Siliconix Incorporated

Chang-Sheng Chen

King Owyang

Frank Kuo

Sen Mao

Mohammed Kasem

Oscar Ou

Serge Jaunay

Peter Wang

Anup Bhalla

Yueh-Se Ho

Jacek Korec

Y Mohammed Kasem

Eddy Tjhia

Bosco Lan

Lee Shawn Luo

A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys

Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys

In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.

Vertical structure for semiconductor wafer-level chip scale packages

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Santa Clara, CA, United States of America

Chang-Sheng Chen