Nan Ya Technology Corporation

Chang-Rong Wu

Chun-I Hsieh

Yi-Nan Chen

Neng-Tai Shih

Tzu-En Ho

Hsin-Jung Ho

Shing-Yih Shih

Kuo-Hui Su

Chih-Hao Chang

Chien-Mao Liao

Chien-Jung Sun

Chung-Yuan Lee

Jeng-Ping Lin

Kuo-Chien Wu

Yinan Chen

Sheng-Wei Yang

Chen-Chou Huang

Chih-Huang Wu

Hung-Chang Liao

Sheng-Tsung Chen

Kaan-Lu Tzou

Chiang-Hung Lin

Teng-Wang Huang

Chih-Han Chang

Wen-Sheng Liao

Yan-Hong Chen

Kou-Chen Liu

Chih-How Chang

Wei-Chia Chen

Seng-Hsiung Wu

Shih-Shu Tsai

Chien-Chang Cheng

Tuz-Ching Tsai

A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.

Method for fabricating magnetoresistive random access memory element

An RRAM includes a resistive layer including a dielectric layer and surplus oxygen ions or nitrogen ions from a treatment on the dielectric layer after the dielectric layer is formed. When the RRAM is applied with a voltage, the oxygen ions or nitrogen ions occupy vacancies in the dielectric layer to increase resistance of the resistive layer. When the RRAM is applied with another voltage, the oxygen ions or nitrogen ions are removed from the vacancies to lower the resistance of the resistive layer.

Method of forming RRAM structure

Magnetoresistive random access memory element and fabrication method thereof

Resistive random access memory structure with tri-layer resistive stack

A method for fabricating an RRAM is provided. First, a bottom electrode is formed. A resistive layer is formed on the bottom electrode. A top electrode is then formed on the resistive layer, wherein the top electrode is selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Finally, the top electrode is irradiated with UV light.

RRAM with improved resistance transformation characteristic and method of making the same

A memory structure includes an active area surrounded by first isolation trenches and second isolation trenches; a bit line trench recessed into the active area of the semiconductor substrate; a word line trench recessed into the active area of the semiconductor substrate and being shallower than the bit line trench. The bit line trench and the word line trench together divide the active area into four pillar-shaped sub-regions. A bit line is embedded in the bit line trench. A word line is embedded in the word line trench. A vertical transistor is built in each of the pillar-shaped sub-regions. A resistive memory element is electrically coupled to the vertical transistor.

1T1R resistive memory device and fabrication method thereof

A single-sided access device includes an active fin structure comprising a source contact area and a drain contact area separated from each other by an isolation region therebetween; a trench isolation structure disposed at one side of the active fin structure, wherein the trench isolation structure intersects with the isolation region between the source contact area and the drain contact area; a sidewall gate disposed under the isolation region and on the other side of the active fin structure opposite to the trench isolation structure so that the active fin structure is sandwiched by the trench isolation structure and the sidewall gate, wherein the sidewall gate has multi-fingers that engage with the active fin structure; and a gate dielectric layer between the sidewall gate and the active fin structure.

Single-sided access device and fabrication method thereof

A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening.

Non-volatile memory cell and fabrication method thereof

A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers.

A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

Method for fabricating semiconductor device having stacked-gate structure

A method for forming a deep trench capacitor buried plate. A substrate having a pad oxide and a pad nitride is provided. A deep trench is formed in the substrate. A doped silicate film is deposited on a sidewall of the deep trench. A sacrificial layer is deposited in the deep trench, and etched back to expose parts of the doped silicate film. Then, an etching process is performed to remove the exposed doped silicate film and parts of the pad oxide for forming a recess. The sacrificial layer is removed. A silicon nitride layer is deposited to fill the recess and to cover the doped silicate film. Finally, a thermal oxidation process is performed to form a doped ion region. The silicon nitride layer is removed. The doped silicate film is removed.

Method for forming a deep trench capacitor buried plate

A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench upon the polysilicon liner.

Trench isolation structure and method of forming the same

A method and structure for forming deep trenches in a semiconductor substrate is provided. The method comprises: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a pad nitride layer on the pad oxide layer; forming a borophosphosilicate glass layer on the pad nitride layer; forming a borosilicate glass layer on the borophosphosilicate glass layer; and forming deep trenches through the borosilicate glass layer, through the borophosphosilicate glass layer, through the pad nitride, through the pad oxide, and into the semiconductor substrate. The borosilicate glass layer and the borophosphosilicate glass layer function as a composite hard mask in forming the deep trenches. With the borophosphosilicate glass layer, the composite hard mask can be easily removed by dry etch process using hydrogen fluoride vapor after the deep trenches have been formed.

Method and composite hard mask for forming deep trenches in a semiconductor substrate

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Taipei, Taiwan

Chang-Rong Wu