United Microelectronics Corp.

United Mociroelectronics Corp.

Chang-Po Hsiung

Nien-Chung Li

Wen-Fang Lee

Shin-Hung Li

Shih-Yin Hsiao

Chih-Chung Wang

Ping-Hung Chiang

Ching-Chung Yang

Tsung-Yu Yang

Shan-Shi Huang

Shih-Chieh Pu

Chia-Lin Wang

Chia-Ling Wang

Chia-Wen Lu

Ssu-I Fu

Chih-Kai Hsu

Yu-Hsiang Lin

Chin-Hung Chen

Chia-Jung Hsu

Chiu-Te Lee

Chun-Ya Chiu

Kai-Kuen Chang

Kuan-Lin Liu

A semiconductor structure comprises a substrate having a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures and second dummy structures and at least a first active region are defined in the first well region by an isolation structure. The first dummy structures are adjacent to the junction and respectively comprise a first metal silicide region and a first doped region of the first conductive type and between the first metal silicide region and the first well region. The first dummy structures are between the second dummy structures and the junction. The second dummy structures respectively comprise a second metal silicide region that direct contacts the first well region.

Semiconductor structure

A semiconductor device is disclosed. The semiconductor device includes a substrate, an active region in the substrate, a recessed region in the active region, a gate dielectric layer on the recessed region, a gate structure on the gate dielectric layer, and a source/drain region in the active region and at a side of the gate structure. An edge portion of the gate dielectric layer comprises a rounded profile, and the source/drain region directly contacts the edge portion of the gate dielectric layer.

Semiconductor device and method for forming the same

A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

High voltage semiconductor device

Manufacturing method of high voltage semiconductor device

A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.

High voltage semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

Semiconductor device and manufacturing method thereof

A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a '-' shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET.

Buried channel metal-oxide-semiconductor field-effect transistor (MOSFET) and forming method thereof

A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

Semiconductor transistor and fabrication method thereof

A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Method of forming transistor with dual spacer

Transistor with dual spacer and forming method thereof

A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

Semiconductor device

A high voltage transistor including a substrate is provided, and the substrate has an indent region. A doped region is disposed in the substrate at both sides of the indent region. A shallow trench isolation (STI) structure is disposed in the doped region of the substrate, at a periphery region of the indent region, wherein a portion of a bottom of the STI structure within the indent region has a protruding part down into the substrate. A gate insulating layer is disposed on the substrate at a central region of the indent region other than the STI structure, wherein the gate insulating layer has a protruding portion. A gate structure is disposed on the gate insulating layer and the STI structure within the indent region, covering the protruding portion of the gate insulating layer.

High voltage transistor and fabrication method thereof

A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

Semiconductor device and method of forming the same

A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.

Growing community of inventors

Hsinchu, Taiwan

Chang-Po Hsiung