Taiwan Semiconductor Manufacturing Comp. Ltd.

Chang-Pin Huang

Hsien-Ming Tu

Yu-Chia Lai

Ching-Jung Yang

Tung-Liang Shao

Hsien-Wei Chen

Hao-Yi Tsai

Shih-Wei Liang

Hung-Yi Kuo

Chen-Hua Douglas Yu

Chung-Shi Liu

Mirng-Ji Lii

Ren-Xuan Liu

Ying-Ju Chen

Tzuan-Horng Liu

Michael Shou-Ming Tong

Chih-Hua Chen

Chun-Hung Lin

Yu-Feng Chen

Chien-Chia Chiu

Bor-Rung Su

The present disclosure provides a method of processing a semiconductor structure. The method includes: placing a first semiconductor structure inside a semiconductor processing apparatus; supplying a solution, wherein the solution is directed toward a surface of the first semiconductor structure, and the solution includes a solvent and a resist; rotating the first semiconductor structure to spread the solution over the surface of the first semiconductor structure; forming a resist layer on the surface of the first semiconductor structure using the resist in the solution; and removing a portion of the solvent from the solution by an exhaust fan disposed adjacent to a periphery of the first semiconductor structure.

Conductive bump of a semiconductor device and fabricating method thereof cross reference to related applications

Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a conductive layer in the substrate, a conductive bump over the substrate and electrically coupled to the conductive layer, and a dielectric stack, including a polymer layer laterally surrounding the conductive bump and including a portion spaced from a nearest outer edge of the conductive bump with a gap, wherein a first thickness of the polymer layer in a first region is greater than a second thickness of the polymer layer in a second region adjacent to the first region, a first bottom surface of the polymer layer in the first region is leveled with a second bottom surface of the polymer layer in the second region, and a dielectric layer underneath the polymer layer.

Conductive bump of a semiconductor device and fabricating method thereof

A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.

Semiconductor device and manufacturing method thereof

Present disclosure provides a semiconductor structure, including a substrate, a pad on the substrate, a conductive layer electrically coupled to the pad at one end, a metal bump including a top surface and a sidewall, a solder bump on the top surface of the metal bump, a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer, and a polymer layer on the top surface of the dielectric layer, the polymer layer being spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap. A method for fabricating a semiconductor device is also provided.

Bump structure and fabricating method thereof

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Package with solder regions aligned to recesses

An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected.

Hollow metal pillar packaging scheme

A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.

Method for manufacturing semiconductor structure

A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad.

Semiconductor device and fabricating method thereof

A semiconductor structure has an integrated circuit component, a conductive contact pad, a seal ring structure, a conductive via, a ring barrier, and a mold material. The conductive contact pad is disposed on and electrically connected with the integrated circuit component. The seal ring structure is disposed on the integrated circuit component and surrounding the conductive contact pad. The conductive via is disposed on and electrically connected with the conductive contact pad. The ring barrier is disposed on the seal ring structure. The ring barrier surrounds the conductive via. The mold material covers side surfaces of the integrated circuit component. A semiconductor manufacturing process is also provided.

Semicondcutor structure and semiconductor manufacturing process thereof

An optical sensing system is disclosed. The optical sensing system includes a printed circuit board (PCB), a supporter and an optical sensor. The PCB includes a top surface, a bottom surface and a through cavity, wherein the through cavity extends downwardly from the top surface to the bottom surface. The supporter has a top surface and a bottom surface. The optical sensor is bonded and coupled to the top surface of the supporter, wherein the optical sensor includes a primary optic structure. Wherein the supporter is flipped over and bonded to the PCB with the top surface facing the through cavity, so that the optical sensor is coupled to the PCB and at least partially extends to the through cavity. Associated electronic devices are also disclosed.

Growing community of inventors

Yangmei, Taiwan

Chang-Pin Huang