Hynix Semiconductor Inc.

Hyundai Motor Company

Kia Motors Corporation

Skhynix Inc.

Chang Jun Park

Seong Cheol Kim

Kwon Whan Han

Sung Min Kim

Ha Na Lee

Min Suk Suh

Chang Han Kim

Hyeong Seok Choi

Jong Hoon Kim

Myeong Hwan Kim

Jae Min Lee

Seung Hyun Lee

Seung Yong Lee

Seung Taek Yang

Keun Soo Kim

Jong Ki Kim

Tac Keun Oh

June Young Park

Sang Joon Lim

Man Seok Oh

Seok Lae Kim

Chang Han Park

A fuel tank venting system for a hybrid vehicle includes a first flow path configured to deliver fuel vaporized from a fuel tank to a canister, a second flow path configured to deliver air used for cooling a high voltage battery to the canister, a first three-way valve disposed on the second flow path and configured to control opening and closing of a first discharge port for releasing pressure of the fuel tank, a second three-way valve disposed on the second flow path and configured to control opening and closing of a second discharge port for flowing the air used for cooling the high voltage battery into the canister or discharging the air used for cooling the high voltage battery outside the vehicle, and a controller configured to control the first three-way valve and the second three-way valve.

Fuel tank venting system for hybrid vehicle

An apparatus and a method for preventing overflow of fuel from a vehicle fuel tank are provided may prevent liquid fuel from overflowing into a canister by for a predetermined time storing liquid fuel, which overflows from a fuel tank through a vent valve while the vehicle is traveling, in a fuel overflow prevention chamber, and by returning the fuel in the fuel overflow prevention chamber to the fuel tank by driving a fuel pump in a reverse direction when an engine is turned off.

Apparatus and method for preventing overflow of fuel from vehicle fuel tank

A fuel heating device may improve cold start performance and solve a number of problems of conventional auxiliary tank and heating systems of a flex fuel vehicle (FFV). The fuel heating device may include a heater having embedded therein a heat emission object for heating fuel, a solenoid valve connected the heater such that a flow path to a first outlet is opened or closed to selectively supply fuel, a temperature sensor installed in the heater, and a controller for turning on and off the heater and opening and closing the solenoid valve according to a temperature of the fuel, in which the outlet of the heater is connected with a cold start injector through a cold start line and an inlet of the solenoid valve is connected with a fuel line connected from the fuel tank.

Fuel heating device for improving cold start performance of flex fuel vehicle

A fuel supply system of a vehicle, may include a fuel tank storing ethanol therein, a main injector installed at an engine to inject the ethanol from the fuel tank, a heater provided to heat the ethanol supplied from the fuel tank to the engine, a cold-starting injector installed at the engine to inject the ethanol heated by the heater, and a valve unit connected to the main injector and the cold-starting injector and performing a switching operation between a state of the ethanol being supplied from the fuel tank to the main injector and a state of the ethanol heated by the heater being supplied to the cold-starting injector.

Fuel supply system of vehicle

A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance.

Semiconductor package with a reduced volume and thickness and capable of high speed operation and method for fabricating the same

A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough.

Semiconductor package having an internal cooling system

A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same

A printed circuit board includes a body part formed with connection pads on a first surface thereof; and a warpage compensating part formed over the first surface of the body part and having a height that increases from edges toward a center of the warpage compensating part so that an upper surface of the warpage compensating part facing away from the first surface of the body part is convex upward. The warpage compensating part comprises conductive layer patterns formed over the first surface of the body part to be electrically connected to the connection pads; and a solder resist formed over the first surface of the body part so as to expose the conductive layer patterns. The height of the solder resist gradually increases from both edges toward a center of the solder resist.

Printed circuit board

A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during gringing. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.

Warpage resistant semiconductor package and method for manufacturing the same

A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.

Semiconductor chip with chip selection structure and stacked semiconductor package having the same

A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad.

Multi-layer stacked wafer level semiconductor package module

A method for manufacturing a semiconductor package includes forming a groove in the portion outside of the bonding pad of a semiconductor chip provided with the bonding pad on an upper surface thereof; forming an insulation layer on the side wall of the groove; forming a metal layer over the semiconductor chip so as to fill the groove formed with the insulation layer; etching the metal layer to simultaneously form a through silicon via for filling the groove and a distribution layer for connecting the through silicon via and the bonding pad; and removing a rear surface of the semiconductor chip such that the lower surface of the through silicon via protrudes from the semiconductor chip.

Method for manufacturing semiconductor package

Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.

Growing community of inventors

Changwon-si, South Korea

Chang Jun Park