United Microelectronics Corp.

Chang-Hung Chen

Chun-Hsien Huang

Yu-Tse Kuo

Shu-Wei Yeh

Shu-Ru Wang

Chun-Yen Tseng

Yi-Ting Wu

Ya-Lan Chiou

Wei-Chi Lee

Han-Tsun Wang

Po-Yu Yang

Cheng-Hsiung Chen

Mu-Kai Tsai

Tsz-Hui Kuo

Tien-Yu Lu

Mei-Ying Fan

Guan-Shyan Lin

Cheng-Tung Huang

Jen-Yu Wang

Ching-Cheng Lung

Po-Chun Yang

Yung-Ching Hsieh

Jian-Jhong Chen

Hsin-Chih Yu

Chih-Wei Tsai

Bo-Chang Li

Jhen-Siang Wu

Jheng-Tai Yan

The invention provides a layout pattern cell of a static random access memory (SRAM), which at least comprises a first SRAM cell, a plurality of gate structures spanning a plurality of fin structures, so as to form a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, a second access transistor, a third access transistor, a fourth access transistor, a first parasitic transistor and a second parasitic transistor located on a substrate, the first parasitic transistor and the first pull-down transistor span the same fin structure, and the fin structure spanned by the first parasitic transistor and the first pull-down transistor is a continuous structure.

Layout pattern for static random access memory

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region and a second cell region and a diffusion region on the substrate extending through the first cell region and the second cell region. Preferably, the diffusion region includes a first H-shape and a second H-shape according to a top view.

Layout pattern of magnetoresistive random access memory

A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

A layout pattern of static random access memory at least includes a substrate, a plurality of fin structures on the substrate, a plurality of gate structures on the substrate and spanning the fin structures to form a plurality of transistors distributed on the substrate, the plurality of transistors include, a first pull-up transistor PU, a first pull-down transistor PD, a second pull-up transistor PU, a second pull-down transistor PD, a first pass gate transistor PG, a second pass gate transistor PG, a first read transistor RPD and a second read transistor RPG, and an additional fin structure, the additional fin structure is located between the fin structure of the first pass gate transistor PGand the fin structure of the second read transistor RPG.

Layout pattern of static random access memory and the manufacturing method thereof

A memory includes (n&#x2212;1) non-volatile cells, (n&#x2212;1) bit lines and a current driving circuit. Each of the (n&#x2212;1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n&#x2212;1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n&#x2212;1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n&#x2212;1) non-volatile cells.

Memory including non-volatile cells and current driving circuit

The present invention provides a layout pattern of a static random access memory (SRAM), comprising at least one substrate, two SRAM units on the substrate, respectively located in a first region and a second region which is adjacent to the first region. Each of the SRAM units includes a first inverter coupled to a second inverter and configured to form a latching circuit, the first inverter includes a first pull-up transistor (PU) and a first pull-down transistor (PD), the second inverter includes a second pull-up transistor (PU) and a second pull-down transistor (PD). A dummy layer crossing the first a region and the second region, and between the PDin the first region and the PDin the second region, and a contact structure on the dummy layer, electrically connected to a voltage source Vss.

A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.

Semiconductor device and semiconductor apparatus

An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

Method of adjusting signal to noise ratio of SRAM and invertor structure

An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

A SRAM cell includes a first pass-gate device and a second-pass gate device comprising a first conductivity type, a first pull-down device and a second pull-down device comprising the first conductivity type, and a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type. The first pass-gate device and the second pass-gate device respectively include first lightly-doped drains (hereinafter abbreviated as LDDs. The first pull-down device and the second pull-down device respectively include second LDDs. And a dosage of the first LDDs is different from a dosage of the second LDDs.

Static random access memory cell and manufacturing method thereof

The present invention provides a layout pattern of an 8-transistor static random access memory (8T-SRAM), at least including a first diffusion region, a second diffusion region and a third diffusion region disposed on a substrate, a critical dimension region being disposed between the first diffusion region and the third diffusion region. The critical dimension region directly contacts the first diffusion region and the third diffusion region, a first extra diffusion region, a second extra diffusion region and a third extra diffusion region disposed surrounding and directly contacting the first diffusion region, the second diffusion region and the third diffusion region respectively. The first, the second and the third extra diffusion region are not disposed within the critical dimension region.

Growing community of inventors

Tainan, Taiwan

Chang-Hung Chen