International Business Machines Corporation

Chandrika Prasad

Roy Rongqing Yu

Eric D Perfecto

H Bernhard Pogge

George E White

Kimberley A Kelly

Madhavan Swaminathan

Bouwe W Leenstra

Keshav B Prasad

Sampath Purushothaman

Laertis Economikos

Chandrasekhar Narayan

Gordon J Robbins

Lewis Sigmund Goldmann

Michael F McAllister

Arthur Gilman Merryman

William Harrington Brearley

Paul F Findeis

James Patrick Wood

RongQing Roy Yu

Voya Rista Markovich

Sung Kwon Kang

Thomas Anthony Wassick

Suryanarayana Kaja

Giulio DiGiacomo

Ajay Prabhakar Giri

Joseph Michael Sullivan

James A McDonald

Richard L Canull

Andrew F Szewczyk

Donald Seton Farquhar

Michel Despont

Kwong Hon Wong

Peter Vettiger

Sudipta Kumar Ray

Mark David Poliks

Mukta S Farooq

Ute Drechsler

Harvey Charles Hamel

Raymond Thomas Galasco

Ananda H Kumar

William Miller

Umar M Ahmad

Balaram Ghosal

John R Pennacchia

James Kuss

Matthew Wayne Oonk

Rebecca P Fleming

Christopher W Cline

Nancy Wagner Hannon

Jeffrey B Danielson

Samuel Lawhorne, Jr

John J Mele

A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Chip and wafer integration process using vertical connections

A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

Process for making fine pitch connections between devices and structure made by the process

A thin film transfer join process in which a multilevel thin film structure is formed on a carrier, the multilevel thin film structure is joined to a final substrate and then the carrier is removed. Once the carrier is removed, the dielectric material and metallic material that were once joined to the carrier are now exposed. The dielectric material is then etched back so that the exposed metallic material protrudes beyond the dielectric material. Also disclosed is a module made by the foregoing process.

Thin film transfer join process and multilevel thin film module

A method is described for forming an integrated structure, including a semiconductor device and connectors for connecting to a motherboard. A first layer is formed on a plate transparent to ablating radiation, and a second layer on the semiconductor device. The first layer has a first set of conductors connecting to bonding pads, which are spaced with a first spacing distance in accordance with a required spacing of connections to the motherboard. The second layer has a second set of conductors connecting to the semiconductor device. The first layer and second layer are connected using a stud/via connectors having spacing less than that of the bonding pads. The semiconductor device is thus attached to the first layer, and the first set and second set of conductors are connected through the studs. The interface between the first layer and the plate is ablated by ablating radiation transmitted through the plate, thereby detaching the plate. The connector structures are then attached to the bonding pads. This method permits fabrication of a high-density packaged device with reduced cost.

Method of fabricating integrated electronic chip with an interconnect device

A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The MEMS has an anchor portion having a conductor therethrough, by which it is connected to a substrate. The chip is attached to the MEMS substrate in a direction normal to the substrate surface, so as to make a conductive path from the chip to the MEMS. The chip may be attached by bonding the conductor to C4 metal pads formed on the chip, or by bonding the conductor to metal studs on the chip. The MEMS substrate may be thinned before attachment to the chip, or may be removed from the underside of the MEMS. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.

Three-dimensional integrated CMOS-MEMS device and process for making the same

A semi-conductor wafer test or burn-in apparatus having spring contacts made from a shape memory metal which plastically deforms under normal test loading and has a transition temperature at or above or at or below the burn-in temperature.

Full wafer test configuration using memory metals

A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Process for forming a multi-level thin-film electronic packaging structure

A process and apparatus are provided for electroplating a film onto a substrate having a top side including a plating surface includes the following steps. Provide a plating tank with an electroplating bath. Provide an anode in the bath. Place a substrate having a plating surface to be electroplated into the electroplating bath connecting surfaces to be plated to a first cathode. Support a second cathode including a portion thereof with openings therethrough extending across the plating surface of the substrate and positioned between the substrate and the anode. Connect power to provide a negative voltage to the first cathode and provide a negative voltage to the second cathode, and provide a positive voltage to the anode.

Process and apparatus for electroplating microscopic features uniformly across a large substrate

A process is described for integrating an optoelectronic chip and a driver chip on a substrate, in which a waveguide is built into the substrate and the chips are joined to the substrate using a stud/via alignment technique. The waveguide structure includes a reflector and a channel for transmitting light emitted by the optoelectronic chip. A stud formed on the substrate is aligned to a via formed in a layer on the chip, aligning the chip so that the light reaches the reflector and enters the waveguide. A driver chip may be mounted on the substrate in close proximity to the optoelectronic chip.

Fabrication of a hybrid integrated circuit device including an optoelectronic chip

A method of making a surface planarization is provided using a separate pre-cut or precured film laminated onto a metallized surface to form planarized dielectric coating. The method comprises the steps of: (a) providing a thin film interconnect module with a polyimide adhesive laminated with a pre-cut or pre-cured polyimide lamination film on the top of the polyimide adhesive, the polyimide lamination film being covered with a glass plate; (b) applying pressure and heat in a synchronized format to ensure a uniform curing and gap filling in the thin film module metal for the adhesive layer; and (c) releasing the glass plate to expose a smooth lamination film surface.

Method of making a lamination and surface planarization for multilayer thin film interconnect

An electronic interconnection assembly having a thin film bonded to either a glass ceramic or to an organic laminate substrate, and a method for attaching a thin film wiring package to the substrate. Provided is the utilization of adhesives which may be processed at significantly lower temperatures so as to avoid damaging components, the wiring package and interconnection joints. Moreover, pursuant to specific aspects, the joining of the thin film to the substrate may be implemented with the utilization of dendrites.

Thin film attachment to laminate using a dendritic interconnection

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Wappingers Falls, NY, United States of America

Chandrika Prasad