Sandisk Corporation

Catalyst Semiconductor, Inc.

Other

Bright Microelectronics, Inc.

Winbond Electronics Corporation

Sandisk Technologies Inc.

Chan-Sui Pang

Yueh Yale Ma

Jeffrey W Lutze

Steve K Hsia

Jun Wan

Christophe J Chevallier

Darrell D Rinerson

Keith R Wald

Christopher J Chevallier

Shouchang Tsao

John D Lattanzi

Jack E Frayer

Compensation voltage(s) are applied to a non-volatile memory system during erase operations to equalize the erase behavior of memory cells. Compensation voltages can compensate for voltages capacitively coupled to memory cells of a NAND string from other memory cells and/or select gates. A compensation voltage can be applied to one or more memory cells to substantially normalize the erase behavior of the memory cells. A compensation voltage can be applied to end memory cells of a NAND string to equalize their erase behavior with interior memory cells of the NAND string. A compensation voltage can also be applied to interior memory cells to equalize their erase behavior with end memory cells. Additionally, a compensation voltage can be applied to one or more select gates of a NAND string to compensate for voltages coupled to one or more memory cells from the select gate(s). Various compensation voltages can be used.

Word line compensation in non-volatile memory erase operations

A method for programming a storage element and a storage element programmed using gate induced junction leakage current are provided. The element may include at least a floating gate on a substrate, an active region in the substrate, and a second gate adjacent to the floating gate. The method may include the steps of: creating an inversion region in the substrate below the floating gate by biasing the first gate; and creating a critical electric field adjacent to the second gate. Creating a critical electric field may comprise applying a first positive bias to the active region; and applying a bias less than the first positive bias to the second gate. The element further includes a first bias greater than zero volts applied to the active region and a second bias greater than the first bias applied to the floating gate and a third bias less than or equal to zero applied to the second gate. The first and third bias are selected to create leakage current in the substrate between the floating gate and the select gate.

Flash memory programming using gate induced junction leakage current

A four-terminal dual-bit double-polysilicon source-side injection flash EEPROM cell, capable of storing two bits of information includes a right junction (which can serve as a cell drain or a source), a left junction (which can serve as a cell source or drain), a select-gate, and two floating gates. The two floating gates are insulated from the select-gate by an inter-gate dielectric. The inter-gate dielectric has a &ldquo;weak region&rdquo; so that during erase-mode electrons can tunnel from the floating gate to the select-gate. The two bits in the cell are to be separately read or programmed, but are to be erased simultaneously. Programming of each bit is achieved through hot-carrier injection, while simultaneous erase of the two bits is achieved through electron-tunneling.

Dual-bit double-polysilicon source-side injection flash EEPROM cell

A four-terminal dual-bit double polysilicon source-side injection flash EEPROM cell, capable of storing two bits of information includes a right junction (which can serve as a cell drain or a source), a left junction (which can serve as a cell source or drain), a select-gate, and two floating gates. The two floating gates are insulated from the select-gate by an inter gate dielectric. The inter-gate dielectric has a &ldquo;weak region&rdquo; so that during erase mode electrons can tunnel from the floating gate to the select-gate. The two bits in the cell are to be separately read or programmed, but are to be erased simultaneously. Programming of each bit is achieved through hot-carrier injection, while simultaneous erase of the two bits is achieved through electron tunneling.

Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell

The present invention is directed at a new nonvolatile memory cell structure, and a new erase method and apparatus for operating this and other nonvolatile memory cells, with special emphasis on source-side injection flash EEPROM cells, which enhances the erase efficiency of the cell. By activating the select-gate terminal of the cell using a negative voltage, it has been found for the first time that the erase performance can be improved. In one preferred embodiment, the present invention provides for three overlapping voltage signals applied to the cell terminals, of which two are negative and one positive. In another preferred embodiment, the memory cell is built on an &ldquo;internal P-well&rdquo; within an isolating N-well on the P-type substrate. In this case, by shifting the memory cell's body potential, the erase-mode uses four overlapping erase signals, two of which are negative, and two positive. With experimental data, it is demonstrated that better &ldquo;magnitude balance&rdquo; has been achieved for the highest erase voltages of opposite polarities. Since only moderate voltages are needed for the erase operation while maintaining the erase speed, the otherwise stringent requirement on transistor breakdown voltages for on-chip charge pumps and driver circuitry can be relaxed.

Method for operating nonvolatile memory cells

A flash memory EEPROM device with a programming current limiting ability operates with six terminals and includes a source-side injection cell and a current limiter in series with the cell at a source region of the cell. During programming, an upper current limit is established for the overall channel current through the cell by controlling the voltage on a serial-gate of the current limiter. A second embodiment of a flash memory EEPROM device is structured with only four operating terminals, and includes a current limiting transistor integrally merged with a source-side injection cell. Merger is accomplished by eliminating the source junction of the injection cell and by combining the select-gate of the injection cell with the serial-gate of the current limiting transistor to create a conjoint select-gate. The unified channel under the conjoint select-gate consists of two channel sub-sections with different threshold adjustment implants and thus different threshold voltages. The first sub-section of this unique channel, adjacent to the injection point of the cell, is doped with a lower threshold adjustment implant dose than that of the second channel sub-section, adjacent to the source of the memory device. The second channel sub-section, or appended channel, in accordance with the second embodiment is fabricated using a dedicated photoresist mask to dope the second sub-section of the select-gate channel with a higher threshold adjustment implant dose than that for the first sub-section.

Programming current limiter for source-side injection EEPROM cells

For negative gate erase and programming of non-volatile floating gate EEPROM devices, large positive or negative voltages from one single negative charge pump and from one single positive charge pump are selectively switched onto a one or more memory sectors of twin-well CMOS negative-gate-erase memory cells. The control gate is negative during erasing and positive during programming. In order for FLASH memories to have minimum layout area, small sectors or arrays of EEPROM cells can be erased all at once using a charge pump which includes two pump capacitors to provide negative voltages to the gate terminals of one or more series PMOS transistors.

Switch driver circuit for providing small sector sizes for negative gate

Disclosed is a EEPROM flash memory array utilizing single transistor cells to provide read/write nonvolatile storage. The array includes a plurality of sectors, each oriented along the word line direction, and the sectors may include one or more word lines. An erase select transistor is provided for each sector and each word line includes a pass gate transistor which assists in both the programming and the erase operations.

Memory array architecture for flash memory

Disclosed is a stacked gate electrically erasable programmable read only memory EEPROM cell which utilizes a floating region and a common pass transistor to provide a cell which is programmable at a relatively low drain voltage and which, in addition, by utilizing a pass transistor, overcomes the programming disturbance and false read problems associated with typical stacked gate memory cells. The cell is constructed such that programming and erasing functions take place at separate locations in the gate oxide. An EEPROM memory cell array, utilizing the above memory cell, is disclosed which provides the ability to achieve both byte erase and block erase as well as byte write capability. Also disclosed is a process for producing such a memory cell and memory array.

High density EEPROM cell and process for making the cell

Disclosed is a nonvolatile memory cell which utilizes a tunnel window to discharge the floating gate at a location spacially displaced from the program path for the cell. Also disclosed is a process for making such a memory cell.

Growing community of inventors

Sunnyvale, CA, United States of America

Chan-Sui Pang