Samsung Electronics Co., Ltd.

Chan Soo Hwang

Seungyoon Lee

Vahid Tarokh

Jae Hyun Kim

Jeongjin Lee

Jae-hee Kim

Eung Sun Kim

Young-Doo Kim

Hyo Sun Hwang

Jong-hyuk Kim

Soon-mok Ha

Sang Wook Kwon

Eun Seok Park

Kyung Hun Jang

Young Tack Hong

Sang-Gyun Woo

Han-Ku Cho

Seung Yoon Lee

In Sun Lee

Suk-joo Lee

Young-Seog Kang

Jeong Jin Lee

Doogyu Lee

Youngsoo Kim

Chang Soon Park

Wei Yu

Hyun Ho Choi

Do Kyoon Kim

Chang Yong Shin

Joon Seong Kang

Hyun-Woo Kim

Kee Chang Lee

Tae Soo Kwon

Ouk Choi

Jaehee Kim

Ki Ho Kim

In-Sung Kim

Minseok Kang

Dong-Seok Nam

Yoon Chae Cheong

Woo Jin Jung

Woo-yong Jung

Jong Ae Park

Jeong-Jin Lee

Sookyung Kim

Taehong Min

Jin-young Yoon

Sangho Yun

Soonmok Ha

Yun-Kyeong Jang

Jinsun Kim

Soon Hwan Cha

Seung-Hwa Oh

Hoduk Cho

Seongbo Shim

Hyungjong Bae

Min-Cheol Kwak

Doo Gyu Lee

A method for fabricating a semiconductor device using an overlay measurement and a semiconductor device fabricated by the method are provided. The method includes forming a lower pattern including a lower overlay key pattern having a first pitch, on a substrate, forming an upper pattern including an upper overlay key pattern having a second pitch different from the first pitch, on the lower pattern, measuring an overlay between the lower overlay key pattern and the upper overlay key pattern, removing the upper overlay key pattern, and after removing the upper overlay key pattern, performing an etching process using the upper pattern as an etching mask.

Method for fabricating semiconductor device

A method of manufacturing an integrated circuit (IC) device, the method including forming an underlayer on a feature layer such that the underlayer includes an acid generator; forming an acid-containing underlayer by generating a first acid from the acid generator; forming a photoresist film on the acid-containing underlayer; generating a second acid in a first area of the photoresist film by exposing the first area of the photoresist film; diffusing the first acid from the acid-containing underlayer into the first area of the photoresist film; and forming a photoresist pattern by developing the photoresist film.

Method of manufacturing integrated circuit device

An operating method of an extreme ultraviolet (EUV) lithography device includes defining a target image to render an illumination system, assigning priorities to respective positions of facets of a pupil facet mirror corresponding to the target image, assigning a mirror according to the assigned priorities using linear programming, generating the illumination system by selecting one of the facets of the pupil facet mirror based on a symmetry criterion, and converting mirror assignment information and source map information corresponding to the selected facet into a form recognizable by an EUV scanner.

Extreme ultraviolet lithography device and method of operating extreme ultraviolet lithography device

An EUV photomask having a main area and a scribe lane area and reflecting EUV light includes a reflective multilayer film and an absorption pattern, wherein the scribe lane area includes first and second lanes, wherein the first lane includes first and second sub-lanes extending in the same direction as an extending direction of the first lane, wherein the first sub-lane includes a first dummy pattern that is a portion of the absorption pattern, and the second sub-lane includes a second dummy pattern that is a portion of the absorption pattern, and when EUV light that is not absorbed by the first and second dummy patterns and is reflected by the reflective multilayer film is irradiated at least twice by overlapping a negative tone photoresist, an amount of light exceeds a threshold dose of light in the negative tone photoresist corresponding to the first lane.

EUV photomask and method of forming mask pattern using the same

A semiconductor device manufacturing system includes a photolithography apparatus that performs exposure. On a semiconductor substrate including a chip area and a scribe lane area. An etching apparatus etches the exposed semiconductor substrate. An observing apparatus images the etched semiconductor substrate. A controller controls the photolithography apparatus and the etching apparatus. The controller generates a first mask pattern and provides the first mask pattern to the photolithography apparatus. The photolithography apparatus performs exposure on the semiconductor substrate using the first mask pattern. The etching apparatus performs etching on the exposed semiconductor substrate to provide an etched semiconductor substrate. The observing apparatus generates a first semiconductor substrate image by imaging the etched semiconductor substrate corresponding to the scribe lane area. The controller generates a second mask pattern based on the first mask pattern and the first semiconductor substrate image, and provides the second mask pattern to the photolithography apparatus.

Semiconductor device manufacturing system

An overlay correcting method capable of optimizing correction of an overlay within a scanner correction limit of a scanner of a scanner system, and a photolithography method, a semiconductor device manufacturing method and the scanner system which are based on the overlay correcting method are provided. The overlay correcting method includes collecting overlay data by measuring an overlay of a pattern; calculating correction parameters of the overlay by performing regularized regression using the overlay data, the regularized regression being based on a correction limit of the scanner such that the correction parameters fall within the correction limit of the scanner; and providing the correction parameters to the scanner.

Overlay correcting method, and photolithography method, semiconductor device manufacturing method and scanner system based on the overlay correcting method

An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

Overlay correction method and semiconductor fabrication method including the same

Provided are an extreme ultraviolet (EUV) exposure apparatus for improving an overlay error in a EUV exposure process, and an overlay correction method and a semiconductor device fabricating method using the exposure apparatus. The EUV exposure apparatus includes an EUV light source; a first optical system configured to emit EUV light from the EUV light source to an EUV mask; a second optical system configured to emit EUV light reflected from the EUV mask to a wafer; a mask stage; a wafer stage; and a control unit configured to control the mask stage and the wafer stage, wherein, based on a correlation between a first overlay parameter, which is one of parameters of overlay errors between layers on the wafer, and a second overlay parameter, which is another parameter, the first overlay parameter is corrected through correction of the second overlay parameter.

EUV exposure apparatus, and overlay correction method and semiconductor device fabricating method using the same

A method for fabricating a phase shift mask includes preparing a transmissive substrate on which a first mask region and a second mask region surrounding the first mask region are defined. In the first mask region, main patterns are formed having a first pitch in a first direction and a second direction perpendicular to the first direction. Each of the main patterns has a first area. In at least one row, assist patterns are formed at the first pitch to surround the main patterns. Each of the assist patterns has a second area less than the first area. In the second mask region, dummy patterns are formed in a plurality of rows. The dummy patterns surround the assist patterns at the first pitch. Each of the dummy patterns has a third area greater than the first area.

Semiconductor device

A method of fabricating a semiconductor device includes providing a substrate including a first region and a second region. The method includes forming a first layer on the substrate. The first layer has a first hole on the first region and a second hole on the second region. The method includes forming a second layer in the first hole and the second hole. The method includes forming a mask pattern on the second region of the substrate. The method includes polishing the second layer to form a pattern in the first hole and an overlay key pattern in the second hole. A top surface of the overlay key pattern is further from the substrate than a top surface of the pattern in the first hole.

Method of fabricating a semiconductor device with an overlay key pattern

A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.

Micro-pattern forming method, capacitor and method of manufacturing the same, semiconductor device and method of manufacturing the same, and electronic system including semiconductor device

Method of fabricating phase shift mask and method of fabricating semiconductor device

A method of correcting an overlay includes: forming a first pattern on a first substrate; forming a second pattern on the first pattern; obtaining a first overlay error profile of the second pattern and obtaining a first overlay correction profile from the first overlay error profile; forming a third pattern on the second pattern; obtaining a second overlay error profile of the third pattern and obtaining a second overlay correction profile from the second overlay error profile; and forming the second pattern on a second substrate, wherein the forming of the second pattern on the second substrate includes: determining whether the second overlay correction profile has a non-correctable model parameter; and when the second overlay correction profile has the non-correctable model, obtaining a preliminary correction profile to correct a position of the second pattern to be formed on the second substrate.

Overlay-correction method and a control system using the same

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Yongin-si, South Korea

Chan Soo Hwang