Applied Materials, Inc.

Cypress Semiconductor Corporation

Chan-Lon Yang

Peter R Keswick

Kenneth S Collins

Jeffrey S Marks

David Walter Groechel

Craig A Roderick

Gerald Z Yin

Jerry Yuen-Kui Wong

Tetsuya Ishikawa

Jay D Pinson, Ii

Masato M Toshima

John R Trow

Michael Robert Rice

Douglas Buchberger

Jerry Yuen Wong

Jon Mohn

Lawrence Chang-Lai Lei

Yuen-Kui (Jerry) Wong

Dan Maydan

David Wingto Cheung

Wai-Fan Yau

Judy H Huang

Lawrence C Lei

David N Wang

Usha Raghuram

Benjamin Schwarz

James E Nulty

Daniel J Arnzen

Kimberley A Kaufman

Kiyoko Ikeuchi

Lien Lee

John M White

Mei Yin Chang

Hyman J Levinstein

Gerald Zheyao Yin

Bo Jin

Mira Ben-Tzur

Ivan Petrov Ivanov

Gorley L Lau

Paul Arleo

Vinay Krishna

Jie Zhang

Haojiang Li

Feng Dai

Jim Nulty

Dan Arnzen

A method for processing a semiconductor topography which includes removing metal oxide layers from the bottom of contact openings is provided. In some embodiments, the method may include etching openings within a dielectric layer to expose conductive and silicon surfaces within the semiconductor topography is provided. In such cases, the method further includes exposing the semiconductor topography to an etch process adapted to remove metal oxide material from the conductive surfaces without substantially removing material from the silicon surfaces. In some cases, the etch chemistry used for the etch process may include sulfuric acid. In addition or alternatively, the etch chemistry may include hydrogen peroxide. In any case, the etch chemistry may be distinct from chemistries used to remove residual matter generated from the etch process used to form the openings within the dielectric and/or the removal of the masking layer used to pattern the openings.

Methods for cleaning contact openings to reduce contact resistance

A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Gate etch process

In one embodiment, a via structure includes a liner, a barrier layer over the liner, and an aluminum layer over the barrier layer. The barrier layer helps minimize reaction between the aluminum layer and the liner, thus helping minimize void formation in the via. The liner and the barrier layer may be deposited in-situ by ionized metal plasma (IMP) physical vapor deposition (PVD). In one embodiment, the liner comprises titanium, while the barrier layer comprises titanium nitride.

Aluminum-filled via structure with barrier layer

A domed plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with etch processes, deposition processes and combined etch/deposition processed. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields.

Plasma reactor using inductive RF coupling, and processes

A domed plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the 10 wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with etch processes deposition processes and combined etch/deposition processed. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields.

The invention is embodied in an RF plasma reactor for processing a semiconductor workpiece, including wall structures for containing a plasma therein, a workpiece support, a coil antenna capable of receiving a source RF power signal and being juxtaposed near the chamber, the workpiece support including a bias electrode capable of receiving a bias RF power signal, and first and second magnet structures adjacent the wall structure and in spaced relationship, with one pole of the first magnet structure facing an opposite pole of the second magnet structure, the magnet structures providing a plasma-confining static magnetic field adjacent said wall structure. The invention is also embodied in an RF plasma reactor for processing a semiconductor workpiece, including one or more wall structures for containing a plasma therein, a workpiece support, the workpiece support comprising a lower electrode, an upper electrode facing the lower electrode and spaced across a plasma generation region of said chamber from said lower electrode, and first and second magnet structures adjacent the wall structure and in spaced relationship with one pole of the first magnet structure facing an opposite pole of the second magnet structure, the magnet structures providing a plasma-confining static magnetic field adjacent said wall structure.

Magnetic confinement in a plasma reactor having an RF bias electrode

A method of forming a semiconductor structure includes filling a trench in a first dielectric layer with a gate material. The first dielectric layer is on a semiconductor substrate, and spacers are in the trench. A semiconductor device formed from this structure includes notched gates.

Structure and method for making a notched transistor with spacers

A plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching oxygen-containing layers overlying non-oxygen-containing layers with high selectivity. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with other etch processes, deposition processes and combined etch/deposition processes. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields. Etching of an oxygen-containing layer overlying a non-oxygen-containing layer can be achieved with high selectivity.

Method for processing substrates using gaseous silicon scavenger

A general method of the invention is to provide a polymer-hardening precursor piece (such as silicon, carbon, silicon carbide or silicon nitride, but preferably silicon) within the reactor chamber during an etch process with a fluoro-carbon or fluoro-hydrocarbon gas, and to heat the polymer-hardening precursor piece above the polymerization temperature sufficiently to achieve a desired increase in oxide-to-silicon etch selectivity. Generally, this polymer-hardening precursor or silicon piece may be an integral part of the reactor chamber walls and/or ceiling or a separate, expendable and quickly removable piece, and the heating/cooling apparatus may be of any suitable type including apparatus which conductively or remotely heats the silicon piece.

Plasma reactor with heated source of a polymer-hardening precursor material

The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus in which a concentration of oxygen at flash striking is greater than a concentration during etching.

Plasma etching method

A method for plasma etching, comprising etching a structure with a plasma prepared from a gas mixture comprising: (i) an etching gas, and (ii) a strained cyclic (hydro)fluorocarbon gas, has a high etch selectivity of oxide versus nitride, and is particularly useful in a SAC etch process.

Selective SAC etch process

A plasma process for etching oxide and having a high selectivity to silicon including flowing into a plasma reaction chamber a fluorine-containing etching gas and maintaining a temperature of an exposed silicon surface within said chamber at a temperature of between 200&deg; C. and 300&deg; C. An example of the etching gas includes SiF and a fluorocarbon gas. The plasma may be generated by a capacitive discharge type plasma generator or by an electromagnetically coupled plasma generator, such as an inductively coupled plasma generator. The high selectivity exhibited by the etch process permits use of an electromagnetically coupled plasma generator, which in turn permits the etch process to be performed at low pressures of between 1 and 30 milliTorr, resulting the etching of vertical sidewalls in the oxide layer.

High temperature silicon surface providing high selectivity in an oxide etch process

Plasma etch processes

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Los Gatos, CA, United States of America

Chan-Lon Yang