Raytheon Company

Chad W Fulk

Andrew Peter Clarke

John J Drab

John L Vampola

Sean P Kilcoyne

David R Rhiger

Jeffrey M Peterson

Christopher Lynn Mears

Jay R Neumann

James Pattison

Stuart B Farrell

Aaron M Ramirez

Barry M Starr

Christopher L Mears

Peter M Randolph

Chad M Althouse

An electrical device includes a substrate, an insulating layer supported by the substrate, and an electrically conductive vertical interconnect disposed in a via hole of the insulating layer. The insulating layer may be configured to provide a coefficient of thermal expansion (CTE) that is equal to or greater than a CTE of the vertical interconnect to thereby impart axial compressive forces at opposite ends of the interconnect. The vertical interconnect may be a hybrid interconnect structure including a low CTE conductor post having a pocket that contains a high CTE conductor contact. At low operating temperatures, the high CTE conductor contact is under tension due to the higher CTE, and thus the high CTE conductor contact relieves strain in the device by void expansion and elongation.

Hybrid pocket post and tailored via dielectric for 3D-integrated electrical device

In one aspect, a method includes forming an electrical path between p-type mercury cadmium telluride and a metal layer. The forming of the electrical path includes depositing a layer of polycrystalline p-type silicon directly on to the p-type mercury cadmium telluride and forming the metal layer on the layer of polycrystalline p-type silicon. In another aspect, an apparatus includes an electrical path. The electrical path includes a p-type mercury cadmium telluride layer, a polycrystalline p-type silicon layer in direct contact with the p-type mercury cadmium telluride layer, a metal silicide in direct contact with the polycrystalline p-type silicon layer, and an electrically conductive metal on the metal silicide. In operation, holes, indicative of electrical current on the electrical path, flow from the p-type mercury cadmium telluride layer to the electrically conductive metal.

Electrical contact fabrication

Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.

Hybrid sensor chip assembly and method for reducing radiative transfer between a detector and read-out integrated circuit

An electro-optical sensor chip assembly (SCA) is provided and includes a read-out integrated circuit (ROIC), a detector including a substrate, a buffer layer, a pixel layer and an array of pixels disposed in the pixel layer and an interconnect layer interposed between the ROIC and the pixel layer and comprising cold welded interconnect posts respectively extendible to the ROIC from the pixels. The detector is penetrable by visible wavelength light propagating from a direct view window formed in the substrate and the buffer layer to one or more of the pixels.

Direct read pixel alignment

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Ventura, CA, United States of America

Chad W Fulk