Samsung Electronics Co., Ltd.

Cha-young Yoo

Jae-hyoung Choi

Young-sun Kim

Jung-hee Chung

Seok-Jun Won

Sung-Tae Kim

Se-hoon Oh

Wan-Don Kim

Wan-don Kim

Jeong-sik Choi

Young-wook Park

Jae-Hyun Joo

Eun-ae Chung

Kwang-Hee Lee

Doo-sup Hwang

Soon-yeon Park

Han-Mei Choi

Han-jin Lim

Yong-Kuk Jeong

Se-Hoon Oh

Seung-hee Nam

Suk-jin Chung

Seung-Hwan Lee

Jin-Won Kim

Jong-Cheol Lee

Jin-Yong Kim

Yun-Jung Lee

Young-Geun Park

Jae-Hyun Yeo

Gab-Jin Nam

Suk-Jin Chung

Kyoung-Ryul Yoon

Dong-Hyun Kim

Ki-chul Kim

Jae-young Ahn

Se-Jin Lee

Chang-seok Kang

Ha-Jin Lim

Woo-Gwan Shim

Jin-il Lee

Hong-bae Park

Ki-Yeon Park

Ki-yeon Park

Dae-Jin Kwon

Byung-Hong Chung

Yun-Seok Kim

Jeong-hee Chung

Kyong-Won An

Dae-Sik Choi

Dong-chul Yoo

Nam-Myun Cho

Jin-tae Noh

Kwan-young Oh

Han-mei Choi

Seok-jun Won

Se-jin Shim

Dong-kyun Park

Yong-kuk Jeong

Gyung-hoon Hong

Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

Methods of forming integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions

Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.

Methods of forming fine patterns for semiconductor device

Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same

Methods of forming a capacitor of an integrated circuit device include forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode. A supporting conductor is formed coupling the lower electrode to the contact plug after forming the lower electrode. A capacitor dielectric layer is formed on the lower electrode and an upper electrode of the capacitor is formed on the capacitor dielectric layer.

Methods of forming integrated circuit devices including a capacitor

Capacitors having composite dielectric layers containing crystallization inhibiting regions

Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.

Method of manufacturing semiconductor device

When a metal layer formed by reaction of a metal source and an oxygen (O) source is deposited, oxidization of a conductive layer disposed under or on the metal layer can be reduced and/or prevented by a method of forming the metal layer and a method of fabricating a capacitor using the same. Between forming the conductive layer and the metal layer, and between forming the metal layer and the conductive layer, a cycle of supplying a metal source, purging, supplying an oxygen source, purging, plasma processing of reduction gas and purging is repeated at least once. In this case, the metal layer is formed by repeating a cycle of supplying a metal source, purging, supplying an oxygen source and purging.

Methods of forming metal layers using oxygen gas as a reaction source and methods of fabricating capacitors using such metal layers

Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions

A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

Methods of fabricating metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode

In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.

Method of forming a dielectric structure having a high dielectric constant and method of manufacturing a semiconductor device having the dielectric structure

Methods of forming a zirconium hafnium oxide thin layer on a semiconductor substrate by supplying tetrakis(ethylmethylamino)zirconium ([Zr{N(CH)(CH)}], TEMAZ) and tetrakis(ethylmethylamino)hafnium ([Hf{N(CH)(CH)}], TEMAH) to a substrate are provided. The TEMAZ and the TEMAH may be reacted with an oxidizing agent. The thin layer including zirconium hafnium oxide may be used for a gate insulation layer in a gate structure, a dielectric layer in a capacitor, or a dielectric layer in a flash memory device.

Methods of forming thin layers including zirconium hafnium oxide and methods of forming gate structures, capacitors, and flash memory devices using the same

Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.

Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate

Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.

Capacitor of semiconductor device and method of fabricating the same

A method of manufacturing a semiconductor device can include forming a tunnel oxide layer on a substrate, forming a floating gate on the tunnel oxide layer and forming a dielectric layer pattern on the floating gate using an ALD process. The dielectric layer pattern can include a metal precursor that includes zirconium and an oxidant. A control gate can be formed on the dielectric layer pattern. The semiconductor device can include the dielectric layer pattern provided herein.

Methods of manufacturing a semiconductor device including a dielectric layer including zirconium

Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

Methods for forming semiconductor devices including thermal processing

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Gyeonggi-do, South Korea

Cha-young Yoo