Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries Singapore Pte. Ltd.

Globalfoundries U.S. Inc.

Catherine B Labelle

Min Gyu Sung

Ruilong Xie

Chanro Park

Yi Qi

Xiuyu Cai

Hoon Sik Kim

Xunyuan Zhang

Xiang Hu

Douglas J Bonser

Habib Hichri

Richard Stephen Wise

Xin Miao

Ajey Poovannummoottil Jacob

Lars W Liebmann

Timothy Joseph Dalton

Su Chen Fan

John Christopher Arnold

Kaushik Arun Kumar

Nicholas C M Fuller

Andre P Labonte

Ravi Prakash Srivastava

Mark V Raymond

Kisup Chung

Gunter Grasshoff

Linus Jang

Christopher Michael Prindle

Daniel T Pham

Vikrant Kumar Chauhan

Sohan Singh Mehta

Mark Kelling

Robert Teagle

Tong Qing Chen

A method of fabricating an interconnect structure of a semiconductor device is provided having a first conductive line and forming a second conductive line over the first conductive line. A via opening is formed in the second conductive line, and the via opening is aligned over the first conductive line. The via opening is filled with a conductive material to form an interconnect via and an upper portion of the interconnect via forms a portion of the second conductive line.

Interconnect structures of semiconductor devices having a via structure through an upper conductive line

A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

Methods of forming a gate cap layer above a replacement gate structure

Methods for a lithographic process used to pattern fins for fin-type field-effect transistors (FinFETs). A first plurality of hardmask sections may be formed, and sacrificial spacers may be formed on vertical sidewalls of the first plurality of hardmask sections. Each of the first plurality of hardmask sections is comprised of a first material. Gaps between the sacrificial spacers are filled with a second material, which is selected to etch selectively to the first material, in order to define a second plurality of hardmask sections each comprised of the second material.

Fin cut with alternating two color fin hardmask

A first and second vertical fin are formed on a substrate structure. A dielectric layer is disposed on the substrate structure and the first and second vertical fins. A work function metal (WFM) layer is disposed on the dielectric layer. A first sidewall spacer and a second sidewall space are formed proximate to the first vertical fin and the second vertical fin, respectively. A lithographic mask is applied to a first area proximate to the first vertical fin including the first vertical fin, and a portion of the WFM layer proximate to the first vertical fin. A portion of the WFM layer proximate to the second sidewall spacer is recessed below an upper surface of the second sidewall spacer. The lithographic mask is removed. A portion of the dielectric layer is removed to produce a wimpy vertical transport device and a nominal vertical transport device on the substrate structure.

Wimpy and nominal semiconductor device structures for vertical finFETs

FinFET devices and methods of fabricating a FinFET device are provided. An exemplary method of fabricating a FinFET device includes providing a semiconductor substrate with a plurality of fins and a multi-layered hardmask stack formed thereover. The multi-layered hardmask stack is patterned to form a patterned multi-layered hardmask stack having a tapered fin masking configuration with a shortened region and an elongated region. A region of fins adjacent to the shortened region is masked with a second mask. The region of fins masked with the second mask is free from the patterned multi-layered hardmask stack. Fins in unmasked areas are etched after forming the second mask. The second mask is removed with at least one layer of the patterned multi-layered hardmask stack remaining after etching the fins in the unmasked areas. End portions of the fins adjacent to the shortened region are etched after removing the second mask.

FinFET devices having fins with a tapered configuration and methods of fabricating the same

A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Raised fin structures and methods of fabrication

One illustrative method disclosed herein includes, among other things, forming a fin-removal masking layer comprised of a plurality of line-type features, each of which is positioned above one of the fins, and a masking material positioned at least between adjacent features of the fin-removal masking layer and above portions of an insulating material in the trenches between the fins. The method also includes performing an anisotropic etching process through the fin-removal masking layer to remove the portions of the fins to be removed.

Hybrid fin cutting processes for FinFET semiconductor devices

A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.

Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices

Formation of semiconductor structures employing selective removal of fins includes, for example, providing a substrate having a first plurality of fins having first hard masks thereon, a second plurality of fins having second hard masks thereon, the first hard mask being different from the second hard mask, depositing a first fill material between lower portions of the first and second fins, depositing a third hard mask layer on the first fill material between the first and second fins, depositing a second fill material on the third hard mask extending between upper portions of the first and second fins, selectively removing the second hard masks and the second fins to form open cavities in the first and second fill material, depositing a third fill material in the opened cavities, and removing the second fill material and the third fill material above the third hard mask to form a fin-cut region.

Formation of semiconductor structures employing selective removal of fins

A method includes forming a plurality of fins above a substrate. A first mask layer is formed above a first subset of the fins. First portions of the fins in the first subset exposed by a first opening in the first mask layer are removed to define, for each of the fins, a first fin segment and a second fin segment, each having a cut end surface. A first liner layer is formed on at least the cut end surface of the first fin segment for each of the fins in the first subset. A second mask layer having a second opening is formed above a second subset of the plurality of fins. An etching process removes second portions of the second subset of fins exposed by the second opening. The first liner layer protects the cut end surface of at least the first fin segment during the removing.

Methods of performing fin cut etch processes for FinFET semiconductor devices and the resulting devices

A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.

Dual-strained nanowire and FinFET devices with dielectric isolation

One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices

Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer.

ARC residue-free etching

An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Growing community of inventors

Wappingers Falls, NY, United States of America

Catherine B Labelle