Globalfoundries Inc.

Carsten Grass

Martin Trentzsch

Jan Hoentschel

Peter Baars

Sven Beyer

Ralf Richter

Richard Carter

Alexander Ebermann

Boris Bayha

Thilo Scheiper

Thorsten E Kammler

Elliot John Smith

Ran Yan

Tom Herrmann

Nicolas Sassiat

Peter Krottenthaler

Andreas Hellmich

Torben Kelwing

Sören Jansen

A semiconductor circuit element includes a first semiconductor device positioned in and above a first active region of a semiconductor substrate and a second semiconductor device positioned in and above a second active region of the semiconductor substrate. The first semiconductor device includes a first gate structure having a first gate dielectric layer that includes a first high-k material, and the second semiconductor device includes a second gate structure having a second gate dielectric layer that includes a ferroelectric material that is different from the first high-k material.

Semiconductor circuit element

The present disclosure provides methods of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element includes a first semiconductor device with a first gate structure disposed over a first active region of a semiconductor substrate and a second semiconductor device with a second gate structure disposed over a second active region of the semiconductor substrate, the first gate structure comprising a ferroelectric material buried into the first active region before a gate electrode material is formed on the ferroelectric material and the second gate structure comprising a high-k material different from the ferroelectric material.

Methods of forming a semiconductor circuit element and semiconductor circuit element

A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.

Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure

A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.

Method of forming a gate mask for fabricating a structure of gate lines

Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Methods for fabricating integrated circuits with isolation regions having uniform step heights

The present disclosure provides a method of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element is formed on the basis of a replacement gate process replacing a dummy gate structure of a semiconductor device of the semiconductor circuit element by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a high-k material that is in the ferroelectric phase. In some illustrative embodiments herein, a semiconductor device is provided, the semiconductor device having a gate structure disposed over an active region of a semiconductor substrate. Herein, the gate structure comprises a spacer structure and a dummy gate structure which is replaced by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a ferroelectric high-k material.

A method for fabricating an integrated circuit includes providing a semiconductor substrate with a pad layer overlying the semiconductor substrate and a photoresist layer overlying the pad layer, exposing the photoresist layer to a split laser beam to form a plurality of parallel linear void regions in the photoresist layer, and etching the pad layer and the semiconductor substrate beneath the plurality of parallel linear void regions to form a plurality of extended parallel linear void regions. The method further includes depositing a first dielectric material over the semiconductor substrate, patterning a photoresist material over the semiconductor substrate to cover a portion of the semiconductor substrate, and etching portions of the pad layer, the first dielectric material, and the semiconductor substrate. Still further, the method includes depositing a second dielectric material into the second void regions.

Methods for fabricating FinFET integrated circuits using laser interference lithography techniques

A method for fabricating an integrated circuit includes providing a semiconductor substrate including a gate electrode structure thereon and sidewall spacers along sidewalls of the gate electrode structure to a first height along the sidewalls, forming a planarizing carbon-based polymer layer over the gate electrode structure and over the sidewall spacers, and etching a portion of the optical planarization layer to expose a top portion the gate electrode structure. Further, the method includes etching an upper portion of the sidewall spacers selective to the gate electrode structure so as to expose the sidewalls of the upper portion of the gate electrode structure and depositing a silicide-forming material over the top portion of the gate electrode structure and the sidewalls of the upper portion of the gate electrode structure. Still further, the method includes annealing the silicide-forming material.

Methods for fabricating integrated circuits with fully silicided gate electrode structures

A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Method of forming a material layer in a semiconductor structure

When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Transistor with embedded strain-inducing material formed in cavities based on an amorphization process and a heat treatment

Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

Metal gate structure for semiconductor devices

When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced.

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Dresden, Germany

Carsten Grass