Intel Corporation

Carolyn R McCormick

Rebecca A Jessep

Daryl A Sato

David W Boggs

Terrance J Dishongh

Mitul Bharat Modi

John H Dungan

Sankara J Subramanian

Patricia A Brusso

Ruben Cadena

Tom E Pearson

Jayne L Mershon

Edward L Martin

Thomas O Morgan

An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

Underfill device and method

An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Flexible core for enhancement of package interconnect reliability

An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Via shielding for power/ground layers on printed circuit board

Methods to shield conductive layer from via. A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Methods for forming via shielding

An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.

Arrangement of vias in a substrate to support a ball grid array

A printed circuit board and a system and method of embedding conductor channels into a printed circuit board. These conductor channels are used to provided increased power to circuits on the printed circuit board, provide shielding for these circuits and provide communications for these circuits. These conductor channels are created by ablating dielectric layers in the printed circuit board and depositing a conductive material therein.

Printed circuit board conductor channeling

According to a method of mounting electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are also described.

Methods of manufacturing via intersect pad for electronic components

A standoff device provides predetermined control of a standoff distance between electrical components mounted together with opposing conductive grid array patterns. In an embodiment, a predetermined electrical function is provided by the device to at least one of the electrical components. The standoff device comprises a plurality of rigid one-piece standoff pins which, in an embodiment, contains one or more stops which buttress against the electrical components to serve as a distancing control structure. In an embodiment, the standoff device is integral with one of the electrical components.

Standoff devices and methods of using same

Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.

Surface mount technology to via-in-pad interconnections

A registration coupon is provided for a printed circuit board or other substrate. The registration coupon may be used to determine a hole-to-outer layer feature registration and a solder mask registration. The registration coupon may include a registration hole provided on the circuit board, a metal pad and an anti-pad provided on the circuit board about the registration hole, and a solder mask covering the metal pad.

Coupon registration mechanism and method

A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Apparatus and method for interconnection between a component and a printed circuit board

An apparatus that includes a substrate, one or more via in pads in the substrate; and one or more vents in at least one of the one or more via in pads, the one or more vents connecting an outer diameter of at least one of the one or more via in pads to a diameter larger than the via.

Vented vias for via in pad technology yield improvements

To mount electronic components on a printed circuit board (PCB), the electrical contacts of the components are coupled to PCB bonding pads that are intersected by via pads. To minimize various defects encountered during solder reflow, while concurrently minimizing PCB area and manufacturing costs, the via pads are formed so that the via holes substantially avoid underlying the solder fillets coupling the component contacts to the PCB bonding pads. In one embodiment, the via pads are formed in the inter-pad space beneath the component; in another embodiment they are offset from the bonding pads. A substrate, an electronic assembly, and an electronic system are described.

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Hillsboro, OR, United States of America

Carolyn R McCormick