International Business Machines Corporation

Carlos Juan Sambucetti

Voya Rista Markovich

Judith Marie Rubino

Peter Alfred Gruber

George Frederick Walker

Ravi F Saraf

Judith Marie Roldan

Daniel C Edelstein

David Hirsch Danovitch

Guy Paul Brouillette

Anthony K Stamper

Sampath Purushothaman

Kevin Shawn Petrarca

Richard Paul Volant

James L Speidell

John Harold Magerlein

John Gerard Gaudiello

Daniel George Berger

William J Amelio

Stephen Roux

Michael Liehr

Eugene John O'Sullivan

Stephen L Tisdale

Donna Jean Trevitt

Gary K Lemon

Sandra Guy Malhotra

John Michael Cotte

Emanuel Israel Cooper

William Thomas Motsiff

Mahadevaiyer Krishnan

Steven Paul Ostrander

Chao-Kun Hu

Roy H Magnuson

Madhav Datta

Robert Rosenberg

Rajesh S Patel

Richard B Booth

David E King

Joseph W Mitchell

Soon-Cheon Seo

Timothy Joseph Dalton

Michael A Gaynes

Steven Alan Cordes

Anilkumar Chinuprasad Bhatt

Thomas R Miller

Yu-Ting Cheng

Maurice McGlashan-Powell

Sherif Ahmed Goma

Horatio Seymour Wildman

Xiaomeng Chen

Stefanie Ruth Chiras

James Russell Bupp

Jeffrey R Marino

Alan D Knight

William H Lawrence

Egon Max Kummer

Cyryl Cabral, Jr

Bruce Lee Humphrey

Cyprian Emeka Uzoh

Alejandro Gabriel Schrott

Lubomyr Taras Romankiw

Da-Yuan Shih

Fuad Elias Doany

Naftali Eliahu Lustig

Stephen Edward Greco

Terrence Robert O'Toole

Bruce Kenneth Furman

Maheswaran Surendra

Michael Wayne Lane

Lisa Jeanine Jimarez

Vlasta A Brusic

Donald W Henderson

Henry Atkinson Nye, Iii

Pedro A Chalco

James Anthony Tornello

Dae Young Jung

John E Heidenreich, Iii

Sol Krongelb

Warren A Alpaugh

Stephen James Kilpatrick

Samuel McKnight

Richard Stuart Zarr

Philippe Mark Vereecken

Mark R Kordus

Richard M Poliak

Dennis L Rivenburgh

Theodore Panasik

Joseph J Van Horn

Robert J Owen

Edward A Giess

Fenton Reed Mc Feely

Zlata Kovac

Arthur Harry Kendall

Merrill W Shafer

Simon M Karecki

Sung-Kwon Kang

Ralph E Parsons

Barbara A Gardineer

Hugo Karl Seitz

Birenda Nath Agarwala

The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer

In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

Reduced electromigration and stressed induced migration of copper wires by surface coating

A ball-limiting metallurgy includes a substrate, a barrier layer formed over the substrate, an adhesion layer formed over the barrier layer, a first solderable layer formed over the adhesion layer, a diffusion barrier layer formed over the adhesion layer, and a second solderable layer formed over the diffusion barrier layer.

Ball limiting metallurgy, interconnection structure including the same, and method of forming an interconnection structure

An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.

Self-aligned corrosion stop for copper C4 and wirebond

A method to selectively metallize polyimide with an all-electroless process.

Means of seeding and metallizing polyimide

A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads including an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; the device chips are joined to the carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

High density area array solder microjoining interconnect structure and fabrication method

A self-aligned process for fabricating a corrosion-resistant conductive pad on a substrate, and a structure that includes an interconnect to allow a terminal connection to the pad. The process generates a metallic layer on an initially exposed metal layer. The metallic layer is electrically conductive and corrosion resistant. The process includes providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process includes providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or alloy on the metal layer. The alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or alloy.

A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.

Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same

A microjoint interconnect structure comprising a dense array of metallic studs of precisely controllable height tipped with a joining metallurgy. The array is produced on a device chip that is to be attached to a carrier, or to a carrier along with other devices, some of which may be selected to have similar interconnect structures so as to form all together an assembled carrier that functions as a complete computing, communications or networking system.

High density raised stud microjoining system and methods of fabricating the same

A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than &frac12; of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.

Method for testing chips on flat solder bumps

A method for forming a quaternary alloy film of Co&mdash;W&mdash;P&mdash;Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H SO rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co&mdash;W&mdash;P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co&mdash;W&mdash;P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co&mdash;W&mdash;P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO dielectric layers.

Method for forming Co-W-P-Au films

In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A&mdash;X&mdash;Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect

A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads. In the bonded assembly, the in-situ polymeric mold layer and the underfill material layer forms a composite underfill to replace a conventional underfill material that must be injected between bonded chip and substrate by a capillary action in a time consuming process.

Method for direct chip attach by solder bumps and an underfill layer

Growing community of inventors

Croton-on-Hudson, NY, United States of America

Carlos Juan Sambucetti