Advanced Micro Devices Corporation

Carl Robert Huster

Timothy J Thurgate

Daniel Sobek

Concetta E Riccobene

Sameer S Haddad

Mark T Ramsbey

Tuan Duc Pham

Emi Ishida

Richard P Rouse

Scott D Luning

Effiong Etukudo Ibok

Judy Xilin An

Donald L Wollesen

Wei Long

Masaaki Higashitani

Ognjen Milic-Strkalj

An asymmetric retrograde HALO Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) includes a semiconductor substrate. A gate is formed over the substrate, the gate defining a channel thereunder in the substrate having a source side and a drain side. A retrograde HALO doped area is formed in the source side of the channel using tilted ion implantation. A source and drain are formed in the substrate adjacent to the source and drain sides of the channel. The asymmetrical doping arrangement provides the specified level of off-state leakage current without decreasing saturation drive current and transconductance.

Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET)

Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

Selective epitaxy to reduce gate/gate dielectric interface roughness

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming source and drain regions that are recessed a prescribed depth below the main surface of the semiconductor substrate. Sidewall spacers and a silicide layer are subsequently formed on the gate electrode stack. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Method of making recessed source drains to reduce fringing capacitance

A method of manufacturing a flash memory device with a controllable amount of gate edge lifting including etching the ends of the tunnel oxide forming a cavity at each end of the tunnel oxide and anisotropically depositing and etching an oxide to form spacers on the sides of the gate stack. The spacers have a predetermined thickness that controls the amount of gate edge lifting. The predetermined thickness is determined during a characterization procedure that can be a computer modeling procedure or it can be determined empirically.

Deposited screen oxide for reducing gate edge lifting

A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a lateral electric field within the channel that generates a depletion layer that has electrons at a bottom portion of the depletion layer and applying a vertical electric field within the channel that has a sufficient strength so that the electrons at the bottom portion of the depletion layer are injected into the charge trapping region.

Method of programming a non-volatile memory cell using a vertical electric field

A semiconductor device exhibiting a super-steep retrograde channel profile to reduce susceptibility to &ldquo;latch up&rdquo; is achieved by forming a high impurity concentration layer on a semiconductor substrate and forming a diffusion cap layer near the surface of the high impurity concentration layer. Subsequently, a low impurity concentration layer is formed on the diffusion cap layer of the high impurity concentration layer. The diffusion cap layer formed between the high and low impurity concentration layers substantially prevents the impurities contained in the high impurity concentration layer from diffusing into the overlying low impurity concentration layer, thereby achieving a super-steep retrograde channel profile.

Epitaxial delta doping for retrograde channel profile

A MOS semiconductor device is formed with reduced parasitic junction capacitance and reduced gate resistance. Embodiments include forming oxide sidewall spacers on side surfaces of openings in a nitride layer exposing the substrate, and performing a channel implant. A thin gate oxide layer is then thermally grown on the exposed portion of the substrate, and a relatively thin polysilicon layer is deposited on the gate oxide layer and the spacers. A metal layer, such as tungsten, is then deposited filling the opening, and planarized, as by chemical-mechanical polishing, using the nitride layer as a polish stop. Source/drain regions are thereafter formed by ion implantation, and the source/drain regions are silicided. The sidewall spacers and the nitride layer block the channel implant from the source/drain areas, thereby reducing parasitic junction capacitance, and the metal layer extending from above the gate oxide layer to the top of the gate reduces gate resistance, thereby increasing the switching speed of the finished device.

MOSFET with metal in gate for reduced gate resistance

A field effect transistor ( ) having a source region ( ) and a drain region ( ) includes a source side halo region ( ) formed at a junction between the source region and a channel region to substantially interrupt off state leakage current. The source side halo region is formed by implanting ( ) first doping ions near the surface at the source side of the channel and implanting ( ) second doping ions deeper in the channel, near the depth of a source extension ( ). In this manner, optimization of leakage current of the field effect transistor is made independent of the drive current of the field effect transistor.

Optimized single side pocket implant location for a field effect transistor

A method of reducing the gate resistance in a semiconductor device forms a gate in the semiconductor device followed by the creation of a silicide region on top of the gate. During the initial formation of the silicide region on the gate, formation of silicide on source/drain areas of the semiconductor device is prevented by a shielding material. The shielding material is then removed and additional silicide is created, forming silicide regions on the source/drains and increasing the thickness of the silicide over the gate, thereby lowering the gate resistance.

Dual silicide process to reduce gate resistance

A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a &ldquo;gate edge lifting&rdquo; profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.

Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing

A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped solid source material on portions of the substrate in which source regions are to be formed and diffusing the dopants from the solid source material into the substrate.

Solid-source doping for source/drain to eliminate implant damage

The method of fabricating the semi-conductor device includes forming a center dielectric region on a substrate. The center dielectric region has a first thickness and the substrate includes a first conductive material. Then, a first plurality of spacers is formed near the center dielectric region. A second conductive material is implanted into the substrate using the first plurality of spacers for alignment. The second conductive material form sources/drains the first plurality of spacers are then removed and a dielectric layer is formed over the substrate and the source/drain regions. The dielectric layer has a second thickness that is less than the first thickness. A second plurality of spacers is formed near the center dielectric region. The second plurality of spacers are conductive and have a third thickness that is substantially equal to the difference of the first and second thickness'. A gate dielectric layer is formed over the substrate, center dielectric region, and second plurality of spacers. Finally, a control gate layer is formed over the gate dielectric layer.

Two bit flash cell with two floating gate regions

A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide on the surface of the flash memory device wherein the silicon nitride plugs minimize gate edge lifting.

Nitride plug to reduce gate edge lifting

A method for manufacturing a field effect transistor (,) includes steps of forming a gate stack (,) on the surface (,) of a semiconductor substrate (,), and defining source/drain regions (,) on either side of the gate stack and a channel region (,) under the gate stack. The channel region has one end (,) proximate a first source/drain region and another end (,) proximate a second source/drain region. The method further includes forming a masking layer (,) on the surface of the semiconductor substrate. The masking layer has a nominal alignment position and a misalignment tolerance. The method still further includes implanting doping ions in the semiconductor substrate to asymmetrically dope the field effect transistor, including selecting a tilt angle and a rotation angle (B, D, F, H) sufficient to ensure shadowing of one end of the channel region from implantation of the doping ions.

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San Jose, CA, United States of America

Carl Robert Huster