Micron Technology Incorporated

Other

Boise State University

Byung Yoon Kim

Si-Woo Lee

Sangmin Hwang

Kyuseok Lee

Mark A Zaleski

Sheng Wei Yang

Shivani Srivastava

Yong Mo Yang

Jongpyo Kim

Hyucksoo Yang

Hyuck Soo Yang

Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include an array of memory cells and a transistor located on a periphery of the array of memory cells. A number of data lines are shown coupled to memory cells in the array, wherein the number of data lines extend over a first metal gate of a transistor in the periphery of the array, where the number of data lines are formed from a second metal, and form a direct interface with the first metal gate.

Metal gate memory device and method

Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complementary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Single crystalline silicon stack formation and bonding to a cmos wafer

Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.

Apparatuses including Finfets having different gate oxide configurations, and related computing systems

An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.

Buried connection line for peripheral area of a memory device

Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

Vertical contacts for semiconductor devices

Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices

Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Single crystalline silicon stack formation and bonding to a CMOS wafer

Devices, systems, and methods for forming twisted conductive lines are described herein. One method includes: forming a first row and a second row of a first number of vertical conductive line contacts, the vertical contacts in each row are arrayed in a first horizontal direction and the first row is spaced from the second row in a second horizontal direction; forming a number of conductive lines with curved portions, each conductive line making contact with alternating conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines with one or more curved portions, each conductive line making contact with the remaining ones of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts that have not been contacted by the first number of conductive lines.

Contacts for twisted conductive lines within memory arrays

Systems, methods, and apparatus including multi-direction conductive lines and staircase contacts for semiconductor devices. One memory device includes an array of vertically stacked memory cells, the array including: a vertical stack of horizontally oriented conductive lines, each conductive line comprising: a first portion extending in a first horizontal direction; and a second portion extending in a second horizontal direction at an angle to the first horizontal direction.

Multi-direction conductive line and staircase contact for semiconductor devices

Methods, apparatuses, and systems related to patterning a material over a sense line contact are described. An example method includes forming a sense line contact pattern at an angle to a sense line direction over semiconductor structures on a substrate, wherein the angle to the sense line direction is formed along a path between a sense line contact in a first sense line column and a sense line contact in a second sense line column. The example method further includes removing a portion of a mask material corresponding to the sense line contact pattern to form sense line contacts.

Contact patterning

An apparatus may comprise an optical detector configured to detect an optical beam reflected from a cantilever. The apparatus may further comprise an optical fiber probe suspended from the cantilever and a piezotube configured to move a sample substance in proximity to the optical fiber probe. The cantilever may be configured to deflect in response to an interfacial force between the sample substance and the optical fiber probe. The apparatus may further comprise a feedback controller communicatively coupled to the optical detector and a semiconductive circuit element abutting the cantilever. In response to detecting movement of the optical beam reflected from the cantilever, the feedback controller may apply a voltage to the semiconductive circuit element, which may reduce deflection of the cantilever. The voltage applied by the feedback controller may indicate a strength of the interfacial force between the sample substance and the optical fiber probe.

Cantilever-based optical fiber probe interfacial force microscope for partial immersion in liquid

A cigarette lighter that discourages humans from smoking which is to emit a prerecorded message each time the cigarette lighter is activated. A typical prerecorded message would be to warn the user that smoking is hazardous to one's health. The prerecorded message can be changed if such is desired.

Growing community of inventors

Boise, ID, United States of America

Byung Yoon Kim