Samsung Electronics Co., Ltd.

Byung-yong Choi

Dong-Gun Park

Choong-Ho Lee

Dong-won Kim

Hye-jin Cho

Chang-Woo Oh

Yun-Gi Kim

Young-mi Lee

Yong-kyu Lee

Tae-Yong Kim

Eun-Suk Cho

Suk-Kang Sung

Choong-ho Lee

Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area. The cell transistor includes a notch gate structure, a first channel region formed on a semiconductor substrate under the notch gate structure, a source region and a drain region formed on both sides of the first channel region, a first gate insulation film formed between the first channel region and the notch gate structure, and a memory layer locally formed on areas adjacent to the source and drain regions between the first channel region and the notch gate structure. At the same time that the cell transistor is formed, a plurality of peripheral circuit transistors including at least one transistor having a different structure from the cell transistor are formed on the peripheral circuit area.

Method of manufacturing semiconductor device having notched gate MOSFET

A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Non-volatile memory device for 2-bit operation and method of fabricating the same

In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Split gate flash memory device having self-aligned control gate and method of manufacturing the same

In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate electrodes, formed at least at surface regions of the sidewalls of the fins between the source and the drain regions.

Multi-bit multi-level non-volatile memory device and methods of operating and fabricating the same

Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial patterns having a groove to open a crossing region of the active region on the charge blocking layer, selectively removing portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer exposed by the opening groove using the sacrificial layer patterns as an etch mask to expose a top surface and side surfaces of the active region, forming a gate dielectric layer on exposed portion of the active region to cover exposed side surfaces of the of charge storage layer, forming a first gate on the gate dielectric layer to fill the groove, removing the sacrificial layer patterns, forming second gates on side surfaces of the first gate, forming isolated local charge storage patterns, charge blocking patterns and tunneling dielectric patterns by selectively removing exposed portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer, and forming a source/drain region on the active region.

Nonvolatile memory device having multi-bit storage and method of manufacturing the same

A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.

Non-volatile memory device and methods of forming the same

A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

Growing community of inventors

Suwon-si, South Korea

Byung-yong Choi