Hyundai Electronics Industries Co. Ltd.

Hynix Semiconductor Inc.

Hyundai Electronics Inc. Co., Ltd.

Byung Jin Ahn

Min Kyu Kim

Ju Yeab Lee

Byung Soo Park

Hee Hyun Chang

Sung Jae Chung

Sheung Hee Park

Hee Youl Lee

Jong Woo Kim

Jae C An

Myong Seob Kim

Jea Hyun Sone

Jea Chun Ahn

The present invention relates to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. According to the present invention, a source region and a drain region are first formed and a tunnel oxide film is then formed. Therefore, it is possible to prevent damage of the tunnel oxide film due to an ion implantation process. Further, independent two channel regions are formed below the floating gate. Thus, it is possible to store data of two or more bits at a single cell. In addition, the tunnel oxide film, the floating gate and the dielectric film having an ONO structure are formed at a given regions. It is thus possible to reduce the steps of a process and improve an electrical characteristic and integration level of a device.

Flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell

There is disclosed a code addressable memory (&ldquo;CAM&rdquo;) cell in a flash memory device. In order to stabilize the operation of the CAM cell in a flash memory device operating at a low voltage, the present invention manufactures a CAM cell in which a floating gate is formed to extend on more than two active regions and more than two cell arrays are connected in parallel commonly using a source region and a drain region. Therefore, the present invention can increase the gate-coupling ration of the CAM cell, thus stabilizing the operation of the CAM cell at a device for low-voltage use.

Code addressable memory cell in a flash memory device

There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that expensive photograph equipments are required and the manufacturing costs are thus increased when defining a floating gate and a control gate in a flash memory cell used in a high-integration flash memory device, the present invention performs an etching process for defining a floating gate with an-isotropic etching process. Therefore, it can minimize the areas of a cell and thus obtain a high-integration device.

Method of manufacturing a flash memory device

Methods of erasing a flash memory device are disclosed. After performing a first erasure operation, the methods perform a second erasure operation wherein an erasure pulse width or an erasure voltage is increased if the number of erased cells is below a predetermined number of erased cells, and wherein an erasure pulse width or an erasure voltage is reduced if the number of erased cell is more than a predetermined number of erased cells.

Method of erasing a flash memory device

An address buffer in a flash memory includes a buffer section for buffering external addresses to select specific sectors in the flash memory, a code storage section for storing a code to select a memory sector in the flash memory, a setting section for outputting internal addresses IA &tilde;IA selecting the memory sector, by using the code outputted from the code storage section and sector select addresses among the external addresses.

Address buffer in a flash memory

A flash EEPROM cell according to the present invention is manufactured in accordance with the following processes: forming a oxide film on a portion of the silicon substrate by means of the LOCOS process using the patterned nitride film as an oxidation preventing layer; dry-etching a portion of the oxide film using the patterned nitride film as the etching mask; forming a tunnel oxide film, forming floating gates of a symmetric structure at the etched face; removing the patterned nitride film; forming source and drain regions by means of the self-aligned ion implantation method using the residual oxide film remaining below the patterned nitride film and the floating gates; removing the residual oxide film; forming a select channel region at this portion by means of the ion implantation process for controlling a threshold voltage; and then forming an interpoly oxide film and a control gate by means of the common processes.

Flash EEPROM cell and method of making the same

A method of programming a flash memory cell which increases programming efficiency and characteristics. A depletion area formed at a source region is extended from a surface portion of a silicon substrate to the bottom portion of the silicon substrate. A minority carrier produced at a trap center existing at the extended depletion area receives energy from a high electric field area formed at the silicon substrate between a select gate and floating gate. The minority carrier is then changed into a hot electron by a voltage applied to a drain region. The electron is injected into a floating gate by a vertical direction electric field formed by a high potential voltage applied to a control gate.

Method of programming a flash memory cell

The flash EEPROM cell of split-gate type according to the present invention can prevent the degradation of the tunnel oxide film of the cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap region between the junction region and the gate electrode when programming and erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film.

Flash eeprom cell

Method of making split gate flash EEPROM cell by separating the

Method of making split gate flash EEPROM cell

The present invention discloses a structure of a transistor in a semiconductor device and a method of manufacturing the same. The present invention manufactures a high voltage transistor by etching a silicon substrate to a depth deeper than that of the field oxide film by a self-aligned wet etching process using the field oxide film as a mask and, thereafter, by forming the first gate electrode which electrically switches ON and OFF between the source region and the drain region by using a gate electrode mask and simultaneously forming a second gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film. Accordingly, the present invention can improve the degree of integration of the device by forming a gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.

Structure of a high voltage transistor in a semiconductor device and

The present invention discloses a split gate type flash EEPROM cell and a method of manufacturing the same which can prevent over-erasure of the flash EEPROM cell and decrease the cell area by forming a floating gate in the form of a spacer on a side wall of a select gate and by forming a control gate to surround the select gate and the floating gate.

Growing community of inventors

Seoul, South Korea

Byung Jin Ahn