Samsung Electronics Co., Ltd.

Byung-Hong Chung

Hyun Kyu Park

Bong-jin Kuh

Jeong-lim Nam

Han-Mei Choi

Sang-Gyun Woo

Yong-Suk Tak

Cha-Won Koh

Yool Kang

Wan-don Kim

Seung-Min Lee

Jai-Hyuk Song

Seok-hwan Oh

Soon-Wook Jung

Hyun-Jeong Yang

Dong-Hyun Kim

Ki-Hyun Hwang

Cha-young Yoo

Young-Hoo Kim

Yun-Seung Shin

Young-sub You

Yun-gi Kim

Yong-woo Hyung

Won-Jin Kim

Jong-sung Lim

Sang-Ryol Yang

Ji-Young Min

Ju-Wan Lim

Sang-ryol Yang

Young-Hee Kim

In-Sun Yi

Bon-young Koo

Jong-Sik Chun

Hyun-ho Jo

Hee-seok Kim

Hung-mo Yang

Young-Ho Koh

Soon-wook Jung

Yong-oon Hwang

Don-young Ku

Hyun-Seok Jang

A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.

Semiconductor device having supporter

Semiconductor device having supporter and method of forming the same

A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.

Integrated circuit devices including electrode support structures and methods of fabricating the same

Methods of forming fine patterns for a semiconductor device include forming a hard mask layer on an etch target layer; forming a carbon containing layer on the hard mask layer; forming carbon containing layer patterns by etching the carbon containing layer; forming spacers covering opposing side walls of each of the carbon containing layer patterns; removing the carbon containing layer patterns; forming hard mask patterns by etching the hard mask layer using the spacers as a first etching mask; and etching the etch target layer by using the hard mask patterns a second etching mask.

Methods of forming fine patterns for semiconductor device

A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.

Method of fabricating nonvolatile memory device

A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.

Method of fabricating non-volatile memory device having separate charge trap patterns

In a method of manufacturing a semiconductor device, a first substrate and a second substrate, which include a plurality of memory cells and selection transistors, respectively, are provided. A first insulating interlayer and a second insulating interlayer are formed on the first substrate and the second substrate, respectively, to cover the memory cells and the selection transistors. A lower surface of the second substrate is partially removed to reduce a thickness of the second substrate. The lower surface of the second substrate is attached to the first insulating interlayer. Plugs are formed through the second insulating interlayer, the second substrate and the first insulating interlayer to electrically connect the selection transistors in the first substrate and the second substrate to the plugs. Thus, impurity ions in the first substrate will not diffuse during a thermal treatment process.

Method of manufacturing a semiconductor device

A wiring structure of a semiconductor device may include an insulation interlayer on a substrate, the insulation interlayer having a linear first trench having a first width and a linear second trench having a second width, the linear second trench being in communication with a lower portion of the linear first trench, the first width being wider than the second width, and a conductive layer pattern in the linear first and second trenches.

Wiring structure of a semiconductor device, method of forming the wiring structure, non-volatile memory device including the wiring structure, and method of manufacturing the non-volatile memory device

Example embodiments provide a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

Nonvolatile memory device and method of manufacturing the same

Provided are a nonvolatile memory device and a method of manufacturing the same. A floating gate electrode of the nonvolatile memory device may have a cross-shaped section as taken along a direction extending along a control gate electrode. The floating gate electrode may have an inverse T-shaped section as taken along a direction extending along an active region perpendicular to the control gate electrode. The floating gate electrode may include a lower gate pattern, a middle gate pattern and an upper gate pattern sequentially disposed on a gate insulation layer, in which the middle gate pattern is larger in width than the lower gate pattern and the upper gate pattern. A boundary between the middle gate pattern and the upper gate pattern may have a rounded corner.

In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.

Dual gate oxide structure in semiconductor device and method thereof

A semiconductor device and a method of forming the semiconductor device are disclosed. The semiconductor device includes: a semiconductor substrate; a patterned floating gate formed on the semiconductor substrate, the patterned floating gate having upper and side parts and corners; and a dielectric layer containing a first oxide layer, a nitride layer and a second oxide layer deposited over the semiconductor substrate and the floating gate. The ratio of the thickness of the first oxide layer in the upper and side parts of the patterned floating gate to the thickness of the first oxide layer in the corners of the patterned floating gate does not exceed 1.4. The semiconductor device has an improved coupling coefficient, and reduced leakage current.

Method of forming semiconductor device containing oxide/nitride/oxide dielectric layer

A non-volatile memory device and a method for manufacturing the same are disclosed. A non-volatile memory device comprises a semiconductor substrate having active areas which extend in a first direction and are repeatedly arranged in a second direction orthogonal to the first direction, a plurality of word lines formed on the semiconductor substrate which extending in the second direction while being repeatedly arranged in the first direction, string select lines adjacent to a first word line and extending in the second direction, ground select lines adjacent to a last word line and extending in the second direction, a first insulating interlayer formed on the resultant structure and comprising a first opening exposing the active area between the ground select lines and a second opening exposing the active area between the string select lines, a bit line contact pad formed in the second opening. A sidewall of the contact pad comprises a negative slope in the first direction and a positive slope in the second direction. A hard mask layer pattern, having the same pattern size as the active area, is formed on the contact pad and the first insulating interlayer. A second insulating interlayer is formed on the hard mask layer pattern and the first insulating interlayer. The second insulating interlayer has a bit line contact hole on the contact pad and thus the process margin is sufficiently achieved.

Non-volatile memory device having a bit line contact pad and method for manufacturing the same

A method of self-aligned shallow trench isolation and a method of manufacturing a non-volatile memory using the same are disclosed. An oxide layer, a first conductive layer and a nitride layer are successively formed on a semiconductor substrate. By using a single mask, the nitride layer, the first conductive layer and the oxide layer are etched to form an oxide layer pattern, a first conductive layer pattern and a nitride layer pattern. Subsequently, the upper portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench. A CVD-oxide layer is deposited on the inner surface of the trench to form a trench inner-wall oxide layer, thereby preventing the formation of a positive profile at the sidewalls of the first conductive layer pattern. The trench inner-wall oxide layer is annealed in an N O or NO atmosphere to form an oxynitride layer at the interface between the substrate and trench inner-wall oxide layer. Finally, a field oxide layer that fills up the trench is formed. Because the trench inner-wall oxide layer is formed by a CVD method to prevent the sidewalls of the first conductive layer pattern from having positive slopes, a conductive residue does not remain during a subsequent gate etching process.

Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device comprising the same

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Seoul, South Korea

Byung-Hong Chung