Samsung Electronics Co., Ltd.

Byoungjae Bae

Jongchul Park

Shin Kwon

Inho Kim

Eunsun Noh

Sangmin Lee

Insun Park

Shin-Jae Kang

Hyungjong Jeong

Dohyung Kim

Junghwan Park

Jeongmin Park

Younghyun Kim

Gwanhyeob Koh

Jungmin Lee

Dong-Hyun Im

Kilho Lee

Ki Woong Kim

Yoonjong Song

Se Chung Oh

Kyungil Hong

Kiseok Suh

Jung-In Kim

JaeHee Oh

Gawon Lee

Myung Jin Kang

Heung Jin Joo

Kyung Rae Byun

Hyunchul Shin

Hyeyoung Park

Jinil Lee

Hyunsoo Shin

Sunglae Cho

Manjin Eom

Kyounghun Ryu

Jaesuk Kwon

Changwoo Sun

Juhyung Seo

Takehiko Fujita

A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.

Semiconductor devices having uppermost interconnection lines protruding beyond top surface of lower insulating layer on cell region

A semiconductor device includes a substrate including a first region and a second region, data storage patterns on the first region and spaced apart from each other in a first direction, an upper insulating layer on the first and second regions and on the data storage patterns, a cell line structure penetrating the upper insulating layer on the first region, extending in the first direction, and electrically connected to the data storage patterns, and an upper connection structure penetrating the upper insulating layer on the second region. The upper connection structure includes an upper conductive line, and upper conductive contacts arranged along a bottom surface of the upper conductive line. The bottom surface of the upper conductive line is located at a height higher than a bottom surface of the cell line structure. A side surface of the cell line structure has a straight line shape continuously-extended.

Semiconductor devices and methods of fabricating the same

A magnetic memory device may include an interlayer insulating layer on a substrate, a bottom electrode contact disposed in the interlayer insulating layer, and a magnetic tunnel junction pattern on the bottom electrode contact. The bottom electrode contact may include a second region and a first region, which are sequentially disposed in a first direction perpendicular to a top surface of the substrate so that the second region is between the first region and the top surface of the substrate. A first width of the first region may be smaller than a second width of the second region, when measured in a second direction parallel to the top surface of the substrate.

Magnetic memory device

Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.

Magnetic memory devices having conductive pillar structures including patterning residue components

A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

Semiconductor device

A method of fabricating a magnetic memory device is provided. The method may include sequentially forming a first magnetic layer, a tunnel barrier layer, and a second magnetic layer on a substrate, forming a mask pattern on the second magnetic layer to expose a portion of the second magnetic layer, forming a capping insulating layer on a sidewall of the mask pattern and the portion of the second magnetic layer, injecting an oxygen ion into the portion of the second magnetic layer through the capping insulating layer to form an oxide layer, anisotropically etching the capping insulating layer to form a capping spacer, and patterning the oxide layer, the tunnel barrier layer, and the first magnetic layer using the mask pattern and the capping spacer.

Magnetic memory device comprising oxide patterns

Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns.

Magnetic memory devices

Methods of manufacturing semiconductor devices using cavities to distribute conductive patterning residue

A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.

Semiconductor device, magnetic memory device, and method of fabricating the same

Provided are apparatus and methods for forming phase change layers, and methods of manufacturing a phase change memory device. A source material is supplied to a reaction chamber, and purges from the chamber. A pressure of the chamber is varied according to the supply of the source material and the purge of the source material.

Apparatus and methods for forming phase change layer and method of manufacturing phase change memory device

Provided are semiconductor devices and methods of fabricating the same. The device may include lower interconnection lines, upper interconnection lines crossing the lower interconnection lines, selection elements disposed at intersections, respectively, of the lower and upper interconnection lines, and memory elements interposed between the selection elements and the upper interconnection lines, respectively. Each of the selection elements may be realized using a semiconductor pattern having a first sidewall, in which a first lower width is smaller than a first upper width, and a second sidewall, in which a second lower width is greater than a second upper width, the first and second sidewalls crossing each other.

Semiconductor device and method of fabricating the same

Methods of forming a variable-resistance memory device include patterning an interlayer dielectric layer to define an opening therein that exposes a bottom electrode of a variable-resistance memory cell, on a memory cell region of a substrate (e.g., semiconductor substrate). These methods further include depositing a layer of variable-resistance material (e.g., phase-changeable material) onto the exposed bottom electrode in the opening and onto a first portion of the interlayer dielectric layer extending opposite a peripheral circuit region of the substrate. The layer of variable-resistance material and the first portion of the interlayer dielectric layer are then selectively etched in sequence to define a recess in the interlayer dielectric layer. The layer of variable-resistance material and the interlayer dielectric layer are then planarized to define a variable-resistance pattern within the opening.

Methods of forming variable-resistance memory devices and devices formed thereby

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Byoungjae Bae