Freescale Semiconductor,inc.

International Business Machines Corporation

Motorola Corporation

Byoung W Min

Leo Mathew

Michael A Mendicino

James David Burnett

Laegu Kang

Hector Adrian Sanchez

Kathleen C Yu

Dechao Guo

Keith Kwong Hon Wong

Cheong Min Hong

Sung-Taeg Kang

Jane A Yater

Venkat Kolagunta

Thekkemadathil V Rajeevakumar

Satya N Chakravarti

Michael G Khazhinsky

Asanga H Perera

Chuck T Le

Qingqing Liang

Jon D Cheek

Sinan Goktepeli

Scott K Pozder

James Kenyon Schaeffer, Iii

Dharmesh Jawarani

Nigel Graeme Cave

Omar Zia

Vance H Adams

Stefan Zollner

David C Sing

Salih M Celik

Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.

Selective gate oxide properties adjustment using fluorine

A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.

Integrated split gate non-volatile memory cell and logic structure

After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Replacement-gate-compatible programmable electrical antifuse

A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.

Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology

An electrically programmable fuse (eFuse) comprises a semiconductor layer, a silicide layer overlying the semiconductor layer, and first and second contact structures electrically coupled to the silicide layer. The first contact structure is configured to function as an anode and the second contact structure is configured to function as a cathode. The eFuse further comprises a back-gate structure disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure. Responsive to (i) a programming voltage potential supplied between the first and second contact structures and (ii) a voltage potential supplied to the back-gate structure, silicide of the silicide layer operates to migrate, with an enhanced migration, into the semiconductor layer from the cathode to the anode with an absence of silicide residue in at least the back-gate structure region of the semiconductor layer between the first and second contact structures.

Effective eFuse structure

An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).

Integrated circuit using FinFETs and having a static random access memory (SRAM)

A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.

SOI semiconductor device with body contact and method thereof

A gate electrode is formed overlying a substrate. A first angled metal implant is performed at a first angle into the substrate followed by performing a second angled metal implant at a second angle. The first angled metal implant and the second angled metal implant form a first current electrode and a second current electrode. Each of the first current electrode and the second current electrode has at least two regions of differing metal composition. A metal layer is deposited overlying the gate electrode, the first current electrode and the second current electrode. The metal layer is annealed to form two Schottky junctions in each of the first current electrode and the second current electrode. The two Schottky junctions have differing barrier levels.

Method of forming a transistor having multiple types of Schottky junctions

A method for forming a body contacted SOI transistor includes forming a semiconductor layer () having a body contact region (), a body access region (), and an active region (). An SOI transistor is formed in the active region by etching a metal gate structure () to have a first portion () formed over the active region, and a second portion () formed over at least part of the body access region. By implanting ions () at a non-perpendicular angle into an implant region () in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide () may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region () in the body access region.

Efficient body contact field effect transistor with reduced body resistance

A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.

Process for forming an electronic device including a fin-type structure

A resistive device () and a transistor () are formed. Each uses a portion of a metal layer () that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer () overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.

Semiconductor device with integrated resistive element and method of making

A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor stack is provided which includes a semiconductor substrate, a first semiconductor layer, and a first dielectric layer disposed between the substrate and the first semiconductor layer. A first trench is formed in the first dielectric layer which exposes a portion of the substrate, and a first implant region is formed in the first trench. Cathode and anode regions are formed in the first implant region.

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Austin, TX, United States of America

Byoung W Min