Samsung Electronics Co., Ltd.

Byong-man Kim

Jo-won Lee

Moon-kyung Kim

In-kyeong Yoo

Soo-doo Chae

Hee-soon Chae

Won-il Ryu

Chung-woo Kim

Mi-young Kim

Won-bong Choi

Yo-sep Min

Insang Song

Nae-Sung Lee

Seok-yeol Yoon

Hyung-lae Roh

Moon-kyoung Kim

A method of manufacturing a memory device includes defining a field region and an active region in a substrate, forming a field oxide layer on the field region, forming an insulating layer on the active region, patterning the insulating layer to form first and second bit lines separated from and parallel to each other on the active region, forming a memory element for storing data in a nonvolatile state, wherein the memory element passes across the first and second bit lines, and forming a word line on the insulating layer and the memory element.

Method of manufacturing a memory device

A rewritable data storage using a carbonaceous material writes or erases information represented by the carbonaceous material by means of a current induced electrochemical reaction on a conductive layer, by controlling a voltage applied across the space between a cantilever tip and the conductive layer. Also, the size of the carbonaceous material representing information is controlled by the level of the applied voltage or the application duration.

Rewritable data storage using carbonaceous material and writing/reading method thereof

A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.

Memory device comprising single transistor having functions of RAM and ROM and methods for operating and manufacturing the same

In a method for manufacturing a single electron memory device including a single electron storage element in a gate lamination pattern formed on a nano-scale channel region of a MOSFET, formation of the gate lamination pattern includes sequentially forming a lower layer and a single electron storage medium for storing a single electron tunneling through the lower layer on a substrate, forming an upper layer including a plurality of quantum dots on the single electron storage medium, forming a gate electrode layer on the upper layer to be in contact with the plurality of quantum dots, and patterning the lower layer, the single electron storage medium, the upper layer, and the gate electrode layer, in reverse order.

Method for manufacturing a single electron memory device having quantum dots between gate electrode and single electron storage element

Memory device including a transistor having functions of RAM and ROM

A high-density information storage apparatus using electron emission and methods of writing, reading and erasing information using the same are provided. The high-density information storage apparatus includes a lower electrode, a photoconductive layer and a recording medium sequentially provided on the lower electrode, a conductive layer converting unit for making the photoconductive layer conductive, a data write and read unit for writing data to the recording medium or reading data from the recording medium, a data loss preventing unit for preventing loss of data during data write and read operations, and a power supply connected to the lower electrode and the data write and read unit, for supplying voltage necessary for reading and writing data.

High-density information storage apparatus using electron emission and methods of writing, reading and erasing information using the same

A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.

Single electron memory device comprising quantum dots between gate electrode and single electron storage element and method for manufacturing the same

A method for etching a metal layer on a scale of nano meters, includes preparing a substrate on which a metal layer is formed, positioning a micro tip over the metal layer, generating an electron beam from the micro tip by applying a predetermined voltage between the metal layer and the micro tip, and etching the surface of the metal layer into a predetermined pattern with the electron beam. Accordingly, it is possible to form an etched pattern by applying a negative bias to a micro tip without applying a strong mechanical force to the micro tip, and heating/melting the metal layer with the use of an electron beam emitted from the micro tip which is negative-biased.

Method for etching metal layer on a scale of nanometers

A multi-value single electron memory using a multi-quantum dot, in which the floating gates (FG) of a EEPROM or a flash memory are formed to act as two quantum dots, and the two quantum dots are applied to multi-value memories, and a driving method of the multi-value single electron memory, are provided. Thus, a multi-value memory can be realized using two quantum dots. Also, an ultra-highly integrated memory of 1 Tb or greater can be realized without encountering a physical limit such as a short channel effect (SCE) caused by scaling down MOSFETs, in contrast to other memories.

Multi-value single electron memory using double-quantum dot and driving method thereof

A single electron transistor using porous silicon, which is fabricated by applying porous silicon having a size of several tens of nanometers obtained by electrochemically etching silicon, and a fabrication method thereof, are provided. In the single electron transistor using porous silicon, silicon pores, each of which has a diameter of 5 nm or less, are fabricated by electrochemically etching a silicon on insulator (SOI) substrate having silicon dioxide (SiO ) in its lower portion using an HF-based solution, and serve as islands of a single electron transistor. Also, a source and a drain are formed of silicon on which metal is deposited or silicon doped with impurities. Hence, formation of islands and tunnel barriers is easy, mass production is possible, and the sizes of islands can be controlled by oxidation, so that single electron transistors capable of operating at room temperature can be easily fabricated.

Single electron transistor using porous silicon and manufacturing method thereof

Single electron transistor using porous silicon

A semiconducting yttrium-barium-copper-oxygen(YBCO) device which locally converts a semiconducting YBCO film to a nonconducting YBCO film by a conductive atomic force microscope (AFM), a superconducting YBCO device which locally converts a superconducting YBCO film to nonsuperconducting YBCO by an AFM, and manufacturing methods thereof are provided. According to a method of manufacturing a semiconducting YBCO device or a superconducting YBCO device locally converted by an AFM tip, a voltage is applied to the local region of a semiconducting YBCO channel or a superconducting YBCO channel by an AFM tip. This can produce a nonconducting YBCO region or nonsuperconducting YBCO region to thereby manufacture a tunnel junction easily without any patterning process by microfabrication including photolithography and dry/wet etching.

Semiconducting YBCO device and superconducting YBCO device locally converted by AFM tip and manufacturing methods therefor

A metal nitride oxide semiconductor (MNOS) type memory using a threshold voltage variation (&Dgr;Vth) due to charging of a single electron when the width of a channel of the memory is set to be smaller than or equal to the Debye screen length (LD) of an electron, and a driving method thereof, are provided. The MNOS memory uses a threshold voltage variation (&Dgr;Vth) due to charging of a single electron occurring when the width of a channel is set to be smaller than or equal to the Debye screen length (LD) which depends on the impurity concentration of a semiconductor substrate.

MNOS-type memory using single electron transistor and driving method thereof

A method of fabricating a single electron tunneling (SET) device, the method including forming a source electrode and a drain electrode a predetermined distance apart from each other on an insulating substrate, forming a metal layer having a thickness on the order of nanometers between the source and drain electrodes, and forming quantum dots between the source and drain electrodes due to the movement of metal atoms/ions within the metal layer caused by applying a predetermined voltage to the source and drain electrodes. In the manufacture of an SET device, quantum dots can be formed by a simple method instead of an self assembled monolayer (SAM) method or lithographic methods. Thus, SET devices fabricated in this way have no material dependency, and are also applicable to large scale integration (LSI) structures. Also, since quantum dots are obtained by deposition and electromigration, SET devices having the above-described advantages can be mass-produced.

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Gunpo, South Korea

Byong-man Kim