Samsung Electronics Co., Ltd.

Byeong-yun Nam

Beom-jun Jin

Young-pil Kim

Hyoung-Joon Kim

Dong-Hyun Kim

Sang-Won Lee

Jin-Hong Kim

Chang-woong Chu

Yong-chul Oh

Chang-jin Kang

Ji-soo Kim

Kyung-won Park

Sang-Hyeop Lee

Joo-tae Moon

Hwa-sook Shin

Byong-sun Ju

Hyoun-woo Kim

A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

Semiconductor device having transistor and method of manufacturing the same

An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby

Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad

Semiconductor device having transistor

Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Methods for forming conductive contact body for integrated circuits using dummy dielectric layer

A method for forming a patterned platinum layer on a microelectronic substrate includes the steps of forming a platinum layer on the microelectronic substrate, and forming a mask layer on the platinum layer. In particular, the mask layer defines exposed portions of the platinum layer, and the mask layer comprises a mask material including titanium. The exposed portions of the platinum layer are then selectively removed to form the patterned platinum layer. Related structures are also disclosed.

Methods for forming patterned platinum layers using masking layers including titanium and related structures

A method of etching a platinum group metal film uses a gas mixture containing argon (Ar), oxygen (O,) and halogen gases and a method of forming a lower electrode of a capacitor uses the etching method. The gas mixture contains O,, Ar, and a third component, preferably a halogen, e.g., chlorine (Cl,) or hydrogen bromide (HBr). In the method of forming a lower electrode, a conductive film containing a metal belonging to a platinum (Pt) group is formed on a semiconductor substrate, a hard mask partially exposing the conductive film is then formed on the conductive film. Then, the exposed conductive film is dry-etched using the hard mask as an etching mask and a three-component gas mixture containing argon (Ar) and oxygen (O,), to form a conductive film pattern beneath the hard mask, and the hard mask is then removed.

Methods of etching platinum group metal film and forming lower electrode of capacitor

Methods of forming field effect transistors include the steps of forming a composite of layers including an amorphous silicon layer (a--Si), a silicon dioxide layer thereon and a silicon nitride layer on the silicon dioxide layer. A polycrystalline silicon conductive layer is then formed on the silicon nitride layer by depositing and patterning polycrystalline silicon. The polycrystalline silicon conductive layer is then oxidized using thermal oxidation techniques to form an oxide outerlayer. During this step, a portion of the polycrystalline silicon conductive layer will be consumed to define a gate electrode. Dopants of first conductivity type are then implanted into a top surface of the silicon nitride layer, using the oxide outerlayer and the gate electrode as a mask, to form relatively lightly doped preliminary source and drain regions in the amorphous silicon layer. The oxide outerlayer is then removed preferably using a buffered oxide etchant (BOE) solution which does not etch silicon nitride. Following this, dopants of first conductivity type are again implanted into the amorphous silicon layer, using the gate electrode as a mask. The second implantation step causes the formation of a field effect transistor having self-aligned source and drain regions, self-aligned lightly doped source and drain region extensions (LDS, LDD) and a channel region therebetween which has the same length as the gate electrode. By forming the channel region to have the same length as the gate electrode, improved device characteristics can be achieved.

Methods of forming thin film transistors having lightly-doped drain and

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Byeong-yun Nam