Samsung Electronics Co., Ltd.

Hyundai Electronics Industries Co. Ltd.

Byeong-Ok Cho

Moon-Sook Lee

Takahiro Yasue

Sang-Hun Jeon

Man-Hyoung Ryoo

Chang-min Park

Jeong-Ho Yeo

Ji-Hye Yi

Suk-Hun Choi

Sung-Wook Hwang

Kyung-Chang Ryoo

Sang-Don Nam

Yoon-Ho Son

Jung-hwan Hah

Sung-Lae Cho

Suk-Ho Joo

Jae-Hee Ha

Won-Sun Kim

Man-hyoung Ryoo

Joo-On Park

Kyung-rae Byun

Sang-Heup Moon

Yasue Takahiro

Seouk-Hoon Woo

A method of inspecting a structure. The method includes preparing preliminary spectrums of reference diffraction intensities according to critical dimensions of reference structures, obtaining a linear spectrum from the preliminary spectrums in a set critical dimension range, radiating light to respective measurement structures formed on a substrate, measuring measurement diffraction intensities of the light diffracted by the measurement structures, and obtaining respective critical dimensions of the measurement structures from the measurement diffraction intensities using the linear spectrum.

Methods of inspecting structures

A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Thin film transistors and methods of manufacturing thin film transistors

Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.

Memory units and related semiconductor devices including nanowires

A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes. A semiconductor channel material having a first conductivity type can be formed on the gate insulation layer. A pair of ohmic contacts can be formed on the semiconductor channel material such that the ohmic contacts cross over both side portions of the first gate electrode, respectively. A pair of Schottky contacts can be formed on the semiconductor channel material such that the Schottky contacts cross over both side portions of the second gate electrode, respectively.

Methods of manufacturing CMOS transistor

Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.

Polymer memory device and method of forming the same

Thin film transistors

Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.

Biosensor using nanoscale material as transistor channel and method of fabricating the same

In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second transistor having a second conductivity type are positioned on the substrate, respectively. The first transistor includes a first gate positioned on a first surface of the channel material through a medium of a gate insulation layer and a pair of ohmic contacts positioned on a second surface of the channel material and crossing over both side portions of the first gate electrode, respectively. The second transistor includes a second gate positioned on the first surface of the channel material through a medium of the gate insulation layer and a pair of Schottky contacts positioned on the second surface of the channel material and crossing over both side portions of the second gate electrode, respectively.

CMOS transistor and method of manufacturing the same

Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.

Nonvolatile memory devices and methods of fabricating the same

Methods of manufacturing memory units, and methods of manufacturing semiconductor devices

An organic memory device may include a stack of an organic material layer and a fullerene layer to provide a data storage element between first and second electrodes. The data storage element may include an organic material layer formed on the first electrode, and a fullerene layer between the organic material layer and the second electrode. Methods of fabricating organic memory devices are also discussed.

Organic memory devices including organic material and fullerene layers

A phase changeable memory cell is provided. The phase changeable memory cell includes a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive plug passing through the lower interlayer dielectric layer. The lower conductive plug is in contact with a phase change material pattern disposed on the lower interlayer dielectric layer. The phase change material pattern and the lower interlayer dielectric layer are covered with an upper interlayer dielectric layer. The phase change material pattern is in direct contact with a conductive layer pattern, which is disposed in a plate line contact hole passing through the upper interlayer dielectric layer. Methods of fabricating the phase changeable memory cell is also provided.

Phase changeable memory cells and methods of forming the same

Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

Methods of forming metal contact structures and methods of fabricating phase-change memory devices using the same

In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.

Phase changeable memory device and method of formation thereof

A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Growing community of inventors

Seoul, South Korea

Byeong-Ok Cho