Applied Materials, Inc.

Byeong Chan Lee

Benjamin Colombeau

Nicolas L Breil

Johanes F Swenberg

Bencherki Mebarki

Steven C H Hung

Theresa Kramer Guarini

Malcolm J Bevan

Tejinder Singh

Andy Lo

Xianmin Tang

Huixiong Dai

Joung Joo Lee

Fredrick Fishburn

A method of forming a contact trench structure in a semiconductor device, the method includes performing a first selective deposition process to form a contact on sidewalls of a trench, each of the sidewalls of the trench comprising a first cross section of a first material and a second cross section of a second material, performing a second selective deposition process to form a metal silicide layer on the contact, performing a first metal fill process to form a contact plug within the trench, the first metal fill process including depositing a contact plug metal material within the trench, performing an etch process to form an opening within the trench, comprising partially etching the contact plug metal material within the trench, and performing a second metal fill process, the second metal fill process comprising depositing the contact plug metal material within the opening.

Void-free contact trench fill in gate-all-around FET architecture

The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.

System and methods for dram contact formation

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

Gate all around I/O engineering

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-&#x3ba; layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-&#x3ba; layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.

Formation of bottom isolation

Method of forming an electronic device with a bottom isolation dielectric between a pair of gate stacks is described. Each of the gate stacks comprises a plurality of gate layers. A sacrificial film having a liner on a top and side thereof is on top of the gate layers. A capping layer is on the top of the liner.

Method of forming a bottom isolation dielectric by directional sputtering of a capping layer over a pair of stacks

Methods and apparatus for processing a substrate. The method, for example, includes directing a stream of material from a PVD source at a first non-perpendicular angle to selectively deposit the material on a top portion of one or more features on the substrate and form a first overhang and a second overhang extending beyond a third sidewall and a fourth sidewall that are arranged parallel and opposite to each other and at non-zero angles to a first sidewall and a second sidewall, the first sidewall and the second sidewall defining a length of the one or more features, and the third sidewall and fourth sidewall defining a width of the one or more features; performing an etch process to selectively remove some of the first sidewall and the second sidewall while keeping the third sidewall and fourth sidewall in intact and maintaining the width of the one or more features.

Growing community of inventors

Pleasanton, CA, United States of America

Byeong Chan Lee