Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Burn-Jeng Lin

Tsai-Sheng Gau

Ching-Yu Chang

Chin-Hsiang Lin

Chrong-Jung Lin

Ya-Chin King

Jaw-Jung Shin

Horng-Huei Tseng

Ru-Gun Liu

Yee-Chia Yeo

Li-Jui Chen

Chenming Hu

Chun-Kuang Chen

David Lu

Jan-Wen You

Yi-Pei Tsai

Li-Chun Tien

Jeng-Horng Chen

Shinn-Sheng Yu

Chien-Hung Lin

Kuei-Shun Chen

Chun-Lin Louis Chang

Hua-Tai Lin

Chih-Ming Ke

Shao-Hua Wang

Jen-Chieh Shih

Bang-Chein Ho

Hsiao-Tzu Lu

King-Chang Shu

Bang-Chien Ho

Mi-Chang Chang

Ru-Gyn Liu

Gue Wuu Hwang

Chien-Ping Wang

Yu-Jun Chou

A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an energy sensing film. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The energy sensing film is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the energy sensing film is contacted with an external energy source, and the induced charge is stored in the floating gate.

Defect measurement method

A method includes applying a first voltage to a source of a first transistor of a detector unit of a semiconductor detector in a test wafer and applying a second voltage to a gate of the first transistor and a drain of a second transistor of the detector unit. The first transistor is coupled to the second transistor in series, and the first voltage is higher than the second voltage. A pre-exposure reading operation is performed to the detector unit. Light of an exposure apparatus is illuminated to a gate of the second transistor after applying the first and second voltages. A post-exposure reading operation is performed to the detector unit. Data of the pre-exposure reading operation is compared with the post-exposure reading operation. An intensity of the light is adjusted based on the compared data of the pre-exposure reading operation and the post-exposure reading operation.

Detection using semiconductor detector

A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.

Micro detector

An apparatus for immersion lithography that includes an imaging lens which has a front surface, a fluid-containing wafer stage for supporting a wafer that has a top surface to be exposed positioned spaced-apart and juxtaposed to the front surface of the imaging lens, and a fluid that has a refractive index between about 1.0 and about 2.0 filling a gap formed in-between the front surface of the imaging lens and the top surface of the wafer. A method for immersion lithography can be carried out by flowing a fluid through a gap formed in-between the front surface of an imaging lens and a top surface of a wafer. The flow rate and temperature of the fluid can be controlled while particulate contaminants are filtered out by a filtering device.

Apparatus for method for immersion lithography

An immersion lithographic systemcomprises an optical surface, an immersion fluidwith a pH less than 7 contacting at least a portion of the optical surface, and a semiconductor structurehaving a topmost photoresist layerwherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structurehaving a topmost photoresist layercomprising the steps of: introducing an immersion fluidinto a space between an optical surfaceand the photoresist layer wherein the immersion fluid has a pH of less than 7, and directing light preferably with a wavelength of less than 450 nm through the immersion fluid and onto the photoresist.

Immersion fluid for immersion lithography, and method of performing immersion lithography

A lens cleaning module for a lithography system having an exposure apparatus including an objective lens is provided. The lens cleaning module includes a scanning stage for supporting a wafer beneath the objective lens. A cleaning module is provided adjacent to the scanning stage for cleaning the objective lens in a non-manual cleaning process.

Lens cleaning module for immersion lithography apparatus

A method, tool, and machine for hardening a photoresist image while the photoresist image is immersed in a liquid.

Resist collapse prevention using immersed hardening

A level adjustment system. The level adjustment system includes an adjustable pin chuck, an evacuation device, a level detection device and a length control device. The adjustable pin chuck includes a base and a variable pin to support a substrate. The base includes a recess and an evacuation channel connected thereto. The variable pin is disposed in the recess. The evacuation device is connected to the evacuation channel to evacuate the recess, such that the substrate is attached to the base and variable pin. The level detection device is disposed on the adjustable pin chuck to detect the horizontality of a target surface of the substrate. The length control device is electrically connected to the level detection device and variable pin. The length control device changes the length of the variable pin to adjust level of the target surface of the substrate according to the detected horizontality.

Level adjustment systems and adjustable pin chuck thereof

A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another embodiment, a first layer is formed over a first side of a substrate and over a second side of the substrate. A second layer is formed over the first layers and the wafer is then flash annealed.

Method of heating semiconductor wafer to improve wafer flatness

An image reversal method is described that removes the etch resistance requirement from a resist. A high resolution resist pattern comprised of islands, lines, or trenches is formed with a large process window by exposing through one or more masks including phase edge masks and optionally with resolution enhancement techniques. A complementary material replacement (CMR) layer comprised of an organic polymer or material such as fluorosilicate glass which has a lower etch rate than the resist is coated over the resist pattern. CMR and resist layers are etched simultaneously to provide an image reversed pattern in the CMR layer which is etch transferred into a substrate. The method avoids edge roughness like bird's beak defects in the etched pattern and is useful for applications including forming contact holes in dielectric layers, forming polysilicon gates, and forming trenches in a damascene process. It is also valuable for direct write methods where an image reversal scheme is desired.

Complementary replacement of material

A method is provided for reducing Critical Dimension (CD) non-uniformity in creating a patterned layer of semiconductor material. Two masking layers are respectively created, the first masking layer comprising a main pattern, an isolated pattern and a dummy pattern, the second masking layer exposing the dummy pattern. Methods of compensating for optical proximity effects and micro-loading, as provided by the invention, are applied in creating the first masking layer. The patterned first masking layer is transposed to an underlying layer creating a first pattern therein. The second masking layer removes the dummy features from the transposed first pattern, creating a second pattern therein comprising a main pattern and an isolated pattern to which compensation for optical proximity effects and micro-loading have been applied. The second pattern serves for additional etching of underlying semiconductor material.

Method to reduce CD non-uniformity in IC manufacturing

A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.

Method for improving the critical dimension uniformity of patterned features on wafers

Growing community of inventors

Hsin-Chu, Taiwan

Burn-Jeng Lin