Texas Instruments Corporation

International Business Machines Corporation

Burhan Ozmat

Robert K Peterson

Perwaiz Nihal

Scott L Jacobs

Henri D Schnurmann

Arthur R Zingher

Robert J Gordon

Maurice T McMahon

Aubrey Chapman

Brian J Love

A method of making semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably said base. The second apertures are caused to extend entirely through the base to separate the packages by punching out the remaining portion of the base disposed in the second apertures. Electrical elements are disposed in the cavity and an overlay is provided over the package providing interconnects to the electrical elements in the cavity. The remainder of the cavity is preferably with a potting composition. Optionally, solder balls can be secured to the interconnects and cooling fins can be provided in the base. The base can also be a thin sheet having plurality cavities which can be sawed apart, the thickness of the sheet being at most about the same as the height dimension of the elements disposed within the cavity.

Integrated circuit packaging

A method of making a semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably cast into said base. The second apertures are caused to extend entirely through the base to separate the packages by punching out the remaining portion of the base disposed in the second apertures. Electrical elements are disposed in the cavity and an overlay is provided over the package providing interconnects to the electrical elements in the cavity. The remainder of the cavity is preferably with a potting composition. Optionally, solder balls can be secured to the interconnects and cooling fins can be provided in the base. The base can also be a thin sheet having plurality cavities which can be sawed apart, the thickness of the sheet being at most about the same as the height dimension of the elements disposed within the cavity.

Integrated circuit packaging method and the package

A thermal core (10) including aluminum layer (12) held between two molybdenum layers (14) for dissipating heat from a plurality of chip carriers (22). Core (10) has the ability to withstand excessive vibrational loads while being lightweight. Bonding molybdenum/aluminum/molybdenum layers (12, 14) creates a core (10) having an increased stiffness factor which surpasses military vibrational requirements. Additionally, due to the low density of porous aluminum layer (12), weight limitations set forth by the military can also be met.

Constraining core for surface mount technology

A system for dissipating heat from semiconductor chips disposed on a substrate which may individually produce differing amounts of heat, the substrate secured to a device uniformly distributing the heat produced by the chips thereover in the form of a metal matrix composite of a thermally conductive material, preferably aluminum or copper, having layers of uniformly spaced fibers, preferably carbon, with a higher thermal conductivity than the metal of the metal matrix and embedded therein. Each layer has a plurality of such fibers in rows, each layer being orthogonal to the layers thereabove and therebelow. Preferably, none of the carbon fibers touch each other. The metal matrix is secured to a heat dissipating structure in the form of a housing having a sponge secured therein. The sponge is preferably of aluminum or copper and has a cellular structure, the cells having interconnecting porosity. The housing contains a fluid inlet and outlet whereby fluid travels through the sponge and withdraws heat from the walls of the sponge cells. In an alternative embodiment, the housing is secured to the metal matrix by means of an aluminum-silicon alloy braze layer which is brazed therebetween. Also, the metal matrix can be coated with a layer of pure aluminum to avoid or minimize corrosion. The sponge can be spaced from the housing walls containing the inlet and outlet to permit inlet fluid to travel through the sponge relatively uniformly throughout its entire volume rather than mainly in the direct path between inlet and outlet.

Heat transfer module for ultra high density and silicon on silicon

A thermal core (10) comprising a graphite layer (12) held between two molybdenum layers (14) for dissipating heat from a plurality of chip carriers 22. Core 10 has the ability to withstand excessive vibrational loads while being light weight. Bonding molybdenum/graphite/molybdenum layers (12, 14) creates a core (10) having an increased stiffness factor which surpasses military vibrational requirements. By using a titanium layer (16) to braze graphite layer (12) and molybdenum layers (14), plating for preventing corrosion attack is not necessary.

An electronic system having a first printed wiring board, a first integrated circuit carrier positionable on the printed wiring board and a substrate having a central portion formed of ceramic material. The substrate central portion has a specific thermal conductivity greater than 1.5.times.10.sup.-5 Wm.sup.2 /g.degree.C. The substrate may comprise a ceramic material formed in combination with a modifier of the type which increases fracture toughness thereby inhibiting crack initiation and growth. In an alternate form of the invention the elctronic system includes a substrate having a central portion formed of ceramic material and first and second opposing surfaces each clad with a metallic layer of predetermined thickness. The combination of the substrate and the bonded wiring boards provide an effective coefficient of thermal expansion to each wiring board which is sufficiently close to the coefficient of thermal expansion of the carriers so as to prevent solder joint cracking during operation of the system.

Ceramic based substrate for electronic circuit system modules

An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connected the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each having coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

Module for packaging semiconductor integrated circuit chips on a base

A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a 'good machine' simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

Method of partitioning, testing and diagnosing a VLSI multichip package

A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.

Growing community of inventors

Dallas, TX, United States of America

Burhan Ozmat