Cavium, Inc.

Marvell Asia Pte., Ltd.

3 Leaf Systems, Inc.

Onramp Bioinformatics, Inc.

Bryan Chin

Richard Eugene Kessler

Wilson Parkhurst Snyder, Ii

Shubhendu Sekhar Mukherjee

Michael S Bertone

Isam Wadih Akkawi

Najeeb Imran Ansari

Paul G Scrobohaci

Jeffrey Schroeder

Michael Carns

David Asher

Frank Henry Worrell

Ahmed Shahid

Mike Bertone

Gerald Lampert

Darren Braun

Wu Ye

Christopher Mikulis

Chris Comis

Leo Chen

Srilatha Manne

Xiaodong Wang

David Kravitz

Chetana Nagendra Keltcher

Krishnan Subramani

Scott A Lurndal

Jean Lozach

Chee Hu

Isam Akkawi

Nitin Prakash

Jeremy Davis-Turak

Timothy Wesselman

Teng Chiang Lin

Roshni Patel

Michael Woodacre

Janakiramanan Vaidyanathan

Yoganand Chillarige

Ali Tajeldin

Andy Wang

Jeff Pangborn

Brian Hunter

The systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. Specifically, the network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. To this end, the network chip is configured to allow the BMC to access a plurality of registers of the network chip via an Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Systems and methods for allowing flexible chip configuration by external entity

A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.

Local instruction ordering based on memory domains

A new approach is proposed that contemplates systems and methods to support flexible reconfiguration of a network chip by an external entity, such as a baseboard management controller (BMC), while maintaining a secured environment for the chip so that it can be booted securely. The network chip is configured to designate one or more of its networking ports to the BMC and allow the BMC to configure the designated networking ports without violating the secure areas of the network chip. The network chip is configured to allow the BMC to access a plurality of registers of the network chip via a Network Controller Sideband Interface (NC-SI) block of the network chip by issuing a plurality NC-SI compliant commands. By configuring the designated networking ports, the BMC is configured to establish a data path to a management software of a platform that includes the network chip though the designated networking ports.

Systems and methods for allowing flexible chip configuration by external entity while maintaining secured boot environment

Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.

Distributed interrupt scheme in a multi-processor system

A method for efficiently processing and storing large data sets associated with a multi-stage bioinformatics analysis of genomic data is disclosed. The present method increases the efficiency of the electronic storage of these large data sets by automatically deleting or compressing intermediate data or a portion of output data and compressing input data, where both deletion and compression are based on predetermined characteristics of said data. When necessary, such data can be recovered using generated metadata associated with the data. Doing so, not only improves the storage efficiency of massively large genomic datasets, but also allows for the consistent reproduction of output data with the re-processing of intermediate data based on information stored in metadata.

Method for managing complex genomic data workflows

Local ordering of instructions in a computing system

A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

Collapsed address translation with multiple page sizes

System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.

Method and apparatus for determining metric for selective caching

A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon device and that are coupled to the serial bus. Each of the processing elements comprises a slave timer. Upon receipt of the global timer value, the processing elements synchronize their respective slave timers with the global timer value. After the timers are synchronized, the global timer sends periodic increment signals to each of the processing elements. Upon receipt of the increment signals, the processing elements update their respective slave timers.

Distributed timer subsystem

One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.

Apparatus and method for distributed instruction trace in a processor system

A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.

Merged TLB structure for multiple sequential address translations

Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.

Distributed timer subsystem across multiple devices

In one embodiment, a processor includes plural processing cores, and plural instruction stores, each instruction store storing at least one instruction, each instruction having a corresponding group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having a plurality of group execution masks and a store execution matrix comprising a plurality of store execution masks. The processor further includes a core selection unit that, for each instruction within each instruction store, selects a store execution mask from the store execution matrix. The core selection unit for each instruction within each instruction store selects at least one group execution mask from the group execution matrix. The core selection unit performs logic operations to create a core request mask. The processor includes an arbitration unit that determines instruction priority among each instruction, assigns an instruction for each available core, and signals the instruction store.

QoS based dynamic execution engine selection

A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller.

Debug interface for multiple CPU cores

Growing community of inventors

San Diego, CA, United States of America

Bryan Chin