Advanced Micro Devices Corporation

Ati Technologies Ulc

Advanced Micro Device, Inc.

Bryan Black

Michael Zhouying Su

Gamal Refai-Ahmed

Joe Siegel

Seth Prejean

Michael S Alfano

Maxat Touzelbaev

Anwar Kashem

Yizhang Yang

Joseph R Siegel

James Michael O'Connor

Warren Fritz Kruger

Aaron John Nygren

Julius Din

Neil McLellan

Lei Fu

Dales Morrison Kent

Michael Bienek

Ronnie Brandon

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information.

Interposer with identification system

Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a first side and a second side opposite the first side. The first side has a first reticle field and a second reticle field larger than the first reticle field. Plural conductor pads are positioned on the first side in the first reticle field. Plural dummy conductor pads are positioned on the first side in the second reticle field and outside the first reticle field.

Interposer with beyond reticle field conductor pads

Various semiconductor workpieces with selective backside metallizations and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor workpiece that has multiple dies. A backside metallization is fabricated on a first die of the dies but not on a second die of the dies.

Semiconductor workpiece with selective backside metallization

A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

Semiconductor chip with thermal interface tape

A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture.

Stacked semiconductor chips with thermal management

Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.

Thermal interface material with support structure

Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.

Data bus inversion coding

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Semiconductor chip device with polymeric filler trench

A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip.

Stacked semiconductor chip device with thermal management circuit board

Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.

Unified data masking, data poisoning, and data bus inversion signaling

A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.

Thermal management of stacked semiconductor chips with electrically non-functional interconnects

A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed.

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Spicewood, TX, United States of America

Bryan Black