Infineon Technologies Ag

Other

Infineon Technologies Sc300 Gmbh & Co., Kg

Bruno Spuler

Alois Gutmann

Uwe Paul Schroeder

Karl Emerson Mautz

Gerhard Kunkel

Thorsten Schedel

Christian Drabe

Anke Krasemann

Ralf Zedlitz

Gabriela Brase

Thomas Morgenstern

Jana Haensel

Barbara Lorenz

Torsten Schneider

Ines Th&uuml;mmel

Manfred Kraxenberger

Mike Armacost

A two-step etch process is used to form a vertical collar oxide within the upper portion of a trench capacitor. The first step uses CF/SiF/Ochemistry and ends when the bottom of the collar within the trench is opened although a thin oxide layer still remains on the surface of the PAD-nitride. The second etch step uses CFchemistry to completely remove the remaining silicon oxide layer. The process provides a good uniformity in thickness of the PAD-nitride layer and sufficient collar oxide thickness in the very top section of the collar oxide. The process is applicable for manufacturing deep trench capacitors for DRAM devices.

Method of forming an isolation layer and method of manufacturing a trench capacitor

A semiconductor device and a method for manufacturing the semiconductor device with a self-aligned contact, is described. A first conductor and a second conductor are formed on the surface of the semiconductor substrate. The first conductor and the second conductor are encapsulated with a first encapsulation and a second encapsulation, respectively. The first encapsulation and the second encapsulation contain titanium oxide, boron nitride, silicon carbide, magnesium oxide or carbon. The first encapsulation and the second encapsulation are suitable as a self-aligning etch mask for etching a self-aligned contact hole between the first conductor and the second conductor.

Semiconductor device with self-aligned contact and method for manufacturing the device

There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.

Method for clamping a semiconductor device in a manufacturing process

A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the indentation. The cavity may be either a trench or a via. A &ldquo;Trench First&rdquo; approach and a &ldquo;Via First&rdquo; approach are described.

Method for forming dual damascene structure

A photoresist system is provided that is easily structurable and is suitable for deep ultraviolet range patterning. An increased etching resistance to oxygen-containing plasma is produced in a lithographically generated photoresist structure by treatment with an etch protectant. The etch protectant includes a silylating agent for chemical reaction with reactive groups of the photoresist. In an embodiment, the photoresist includes a base resin initially containing no aromatic groups. Silylating agents include silicon tetrachloride, silicon tetrafluoride, trichlorosilane, dimethylchlorosilane and hexamethyldisilazane.

Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning

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Munich, Germany

Bruno Spuler