Unity Semiconductor Corporation

Kilopass Technology, Inc.

Tc Lab, Inc.

Microunity Systems Engineering, Inc.

Rambus Inc.

Hefei Reliance Memory Limited

Tram, Inc.

T-ram Semiconductor, Inc.

Bruce Lynn Bateman

Harry Luan

Valery Axelrad

Charlie Cheng

Christophe J Chevallier

Chang Hua Siau

David A Eggleston

Louis C Parrillo

Lidia Vereen

John Peter Moussouris

Craig C Hansen

Darrell Rinerson

Deepak Chandra Sekar

Brent Steven Haukness

Elizabeth Friend

Adrian E Ong

Farid Nemati

Frank Guo

An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2Fmay be realized.

Vertical cross-point arrays for ultra-high-density memory applications

A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

3D memory array clusters and resulting memory architecture

A method of writing data into a volatile thyristor memory cell array and maintaining the data with refresh is disclosed.

Thyristor volatile random access memory and methods of manufacture

A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations

A memory device may include a local bit line electrically coupled to a plurality of memory cells and a global bit line electrically coupled to the local bit line through first and second selectable parallel paths having first and second impedances, respectively. The first path may be active and the second path may be in an off state in at least one of a set operation or a forming operation. The second path may be active in a reset operation, wherein the second impedance of the second path has a lower impedance than the first impedance of the first path.

Reduced current memory device

Aspects of DDR and thyristor memory cell RAMs are optimally combined for high-speed data transfer into and out of RAMs. After a Read operation in which data from a selected row of memory cells in an array are latched, a Burst operation selectively moves the latched data from the array or latches external data. At the same time as the Burst data transfer, all the memory cells of the selected row are turned off or on by a write operation. In the following Write-Back & Pre-charge operation, the latched data bits which are complementary to the memory cell state of the Burst write operation are written back into the corresponding memory cells in the selected row. As part of a DDR-like activation cycle, data can be transferred to and from the memory cell array RAM at high-speed.

High-speed data transfer periods for thyristor memory cell arrays

Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various techniques including encoding the data stored in the arrays.

Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. A first voltage is applied across a first group of memory cells for the operation and a lower second voltage is applied across other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells and repeated until the operations covers all the groups.

A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2Fmay be realized.

Vertical cross-point memory arrays

A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Methods of reading and writing data in a thyristor random access memory

In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell.

Growing community of inventors

Fremont, CA, United States of America

Bruce Lynn Bateman