Oracle International Corporation

Sun Microsystems, Inc.

Bruce J Chang

John D Pape

Fred Tsai

Ashley N Saulsbury

Ricky C Hetherington

Bruce E Petrick

Brian McGee

David M Kahn

Damien Walker

Systems and methods for use in enhancing and dynamically allocating random data bandwidth among requesting cores in multi-core processors to reduce system latencies and increase system performance. In one arrangement, a multicore processor includes a vertical pre-fetch random data buffer structure that stores random data being continuously generated by a random data generator (RNG) so that such random data is ready for consumption upon request from one or more of a plurality of processing cores of the multicore processor. Random data received at one data buffer from a higher level buffer may be automatically deposited into the lower level buffer if room exists in the lower level buffer. Requesting strands of a core may fetch random data directly from its corresponding first level pre-fetch buffer on demand rather than having to trigger a PIO access or the like to fetch random data from the RNG.

Acceleration and dynamic allocation of random data bandwidth in multi-core processors

A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.

Dynamic skew correction in a multi-lane communication link

Systems and methods that allow for dynamically deconfiguring, reconfiguring and/or otherwise configuring nodes (e.g., processors) in a symmetric multiprocessing system (e.g., a symmetric multiprocessor) in a manner that avoids, or at least limits, inefficiencies such as renumbering of node IDs, system reboots, SW configuration handle changes, and the like. In one arrangement, a number of modules, tables and/or the like that are configured to generate node IDs and/or convert node IDs from one form to another form can be intelligently implemented within an SMP to allow the various processes and/or components of an SMP to utilize the node IDs in a more efficient manner. For instance, as SDs in an SMP are often configured to work with CNIDs (e.g., for use in determining at which node a particular requested cache line resides), any node GNIDs that are sent to the SD for processing can first be converted into corresponding CNIDs.

Dynamic node configuration in directory-based symmetric multiprocessing systems

A processor employing device-specific memory address translation. In one embodiment, a processor may include a device interface configured to receive a memory access request from an input/output (I/O) device, where the request specifies a virtual memory address and a first requestor identifier (ID) that identifies the I/O device. The processor may also include an I/O memory management unit coupled to the device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to the virtual memory address is stored within an I/O memory translation buffer. The I/O memory management unit may be further configured to determine whether a second requestor ID stored within the I/O memory translation buffer and corresponding to the memory address translation matches the first requestor ID. If the first and second requestor IDs do not match, the I/O memory management unit may disallow the memory access request and to signal an error condition.

Growing community of inventors

Saratoga, CA, United States of America

Bruce J Chang