Unisys Corporation

Bruce Ernest Whittaker

Saul Barajas

Leland E Watson

James Henry Jeppesen, Iii

David M Kalish

James H Jeppesen, Iii

Donald M Kalish

Scott Lane Brock

Stephanie Ninh Truong

Keith S Saldanha

An embodiment of the present invention is a technique for recording relevant information in a graphical user interface (GUI) window. Relevant information on an analysis window is saved in a summary report array using one of an automatic recording mode and a selective recording mode. The analysis window is part of the GUI to analyze state information from a panel dump file retrieved from a computer system. The saved relevant information is displayed on a report window.

Recording relevant information in a GUI window of a panel dump browser tool

An embodiment of the present invention is a technique to provide a graphical user interface (GUI) to analyze memory operations in a computer system. A job summary window shows state information of jobs in at least a unit panel. The unit panel represents at least a functional unit in the computer system. A memory job window shows state information of memory jobs in a functional unit selected from the unit panel to provide diagnostic information to the user. The state information being obtained from a panel dump file retrieved from the computer system.

Automatic analysis of memory operations using panel dump file

An embodiment of the present invention is a technique for providing a graphical user interface (GUI) to view system state of a computer system. An error window displays an error condition of a failed unit in a plurality of functional units in a computer system based on a panel dump file. A warning window shows a warning condition that potentially causes a problem in analyzing system state of the computer system or the error condition.

Displaying abnormal and error conditions in system state analysis

A digital data transport system where a serial stream of digital input data, received from a remote transmitter at an original clock frequency F,, enters a FIFO repository at a variable frequency bit rate having an average frequency rate of I,. A difference generator G, operating at the I,frequency rate, receives a first feedback frequency clock signal F,from a voltage controlled oscillator and a second feedback signal designating the current loading of the FIFO to provide a variable pulse stream to a driver whose output voltage controls the voltage controlled oscillator output frequency F,so that it will match the average input frequency bit rate I,(less the header bytes) in order to approximate the original clock frequency F,.

Control system for recreating of data output clock frequency which matches data input clock frequency during data transferring

A method for compressing a plurality of contiguous addresses for storage in a queue. The method includes recognizing that a first address of the plurality of addresses is an individual address that corresponds to a memory location that is transferred individually. A first value of a block identifier bit is associated with the first address, with the first value identifying the first address as an individual address. The first address and the first value of the block identifier bit are stored into the queue. A further address of the plurality of addresses is recognized as a block address corresponding to a plurality of contiguous data words that reside at a respective plurality of contiguous addresses, that begin with the further address, and that are transferred as a block unit. A second value of the block identifier bit is associated with the further address, the second value identifying the further address as a block address. The second value of the block identifier bit and only the further address of the plurality of contiguous addresses are stored into the queue, thereby compressing the plurality of addresses stored in the queue.

Apparatus and method for compressing a plurality of contiguous addresses

A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations.

Processor bus traffic optimization system for multi-level cache

A method for using linear functions with counter modules for efficient implementation in PALs (Programmable Array Logic), or FPGAs (Field Programmable Gate Arrays) which generate digital control signals to a targeted digital device. An input setting pulsed digital signal A is upcounted and then is reduced by a downcounted feedback pulsed digital signal to produce a difference digital signal which involves adding an intercept value. The difference signal is multiplied by a slope-sensitivity parameter, each time expanding the numeric range and scope of the output digital control signal to the target digital device.

Linear function generator method with counter for implementation of

A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations. Utilization is made of a smart-fill algorithm which selects the address locations for placement of new data in a second level cache for a Write operation and after a Read-Miss by analyzing the status values (V,R) for each address in order to minimize the overwriting of valid cache data.

A 'bit-sliced' construction of our cache module dictates dual TAG RAM structures and dual invalidation queues, yielding enhanced performance. By putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values, processor operations and invalidation operations can be 'overlapped', and even operate simultaneously.

Methods for accessing coincident cache with a bit-sliced architecture

A system and method for developing a digital control signal Y for setting a target module (D) according to a digital setpoint signal A, a digital feedback signal C, a difference digital signal X=A-C in an exponential relationship, such that Y=2.sup.X+1 -1. An N bit digital signal X is translated exponentially via a simple, non-complex programmable array logic unit to an expanded N+q digital bit signal providing an exponentially expanded response for the control signal Y to reset the target module D to an optimally desired setting.

Exponential functional relationship generator method and system for

A system and method in a digital network for developing a digital output control signal Y which is of greater range and sensitivity than an input digital difference signal X wherein Y has a linear functional relationship to X according to a slope parameter 'b'. A method is developed for implementing the network with Field Programmable Gate Arrays (FPGAs) to develop the output control signal Y equal to a+bX on an expanded digital bus, where 'a' is the intercept value of Y when X=0.

Digital device control method and system via linear function generator

A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all the necessary operating addresses and data which can be rapidly transferred via a special wide parallel high speed data bus to a data path array unit for subsequent conveyance to a channel microcode block in a main memory module. The operating data include channel microcode data necessary for the I/O Module to communicate with different types of peripheral devices.

Fast write initialization method and system for loading channel adapter

A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

Processor path emulation system providing fast readout and verification

A multi-set cache structure, providing a first-level cache and second level cache to a processor, stores data words where each word holds two bytes and two status bits. Each cache set includes a Tag RAM for holding the address data words and a Parity RAM holding a parity bit for each byte and a parity bit for the two status bits. A programmable array logic control unit has a predictive generator logic unit to generate the proper 'status parity bit' for each set of status bits (V,R) without need for waiting to calculate the status parity bit from the existing values of the two status bits.

Multi set cache structure having parity RAMs holding parity bits for tag

A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

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Mission Viejo, CA, United States of America

Bruce Ernest Whittaker