Fairchild Semiconductor Corporation

Bruce Douglas Marchant

Dean E Probst

Steven Paul Sapp

Hamza Yilmaz

Christopher Boguslaw Kocon

Thomas E Grebs

Ashok Challa

Nathan Lawrence Kraft

Rodney S Ridley

Joseph Andrew Yedinak

Daniel S Calafut

Gary M Dolny

James J Murphy

Becky Losee

Robert Herrick

Daniel Marvin Kinzer

Paul Thorup

Alan Elbanhawy

Peter H Wilson

Ihsiu Ho

Gordon K Madson

John Tracey Andrews

Babak S Sani

Debra S Woolsey

Duc Q Chau

Thomas P Welch

A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.

Methods related to power semiconductor devices with thick bottom oxide layers

A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.

Trench-gate field effect transistor

In one general aspect, a method of forming a field effect transistor can include forming a well region in a semiconductor region of a first conductivity type where the well region is of a second conductivity type and has an upper surface and a lower surface. The method can include forming a gate trench extending into the semiconductor region to a depth below a depth of the lower surface of the well region, and forming a stripe trench extending through the well region and into the semiconductor region to a depth below the depth of the gate trench. The method can also include forming a contiguous source region of the first conductivity type in the well region where the source region being in contact with the gate trench and in contact with the stripe trench.

Method of forming a dual-trench field effect transistor

A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Method of forming a topside contact to a backside terminal of a semiconductor device

A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region.

LDMOS with self aligned vertical LDD backside drain

A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.

Structure and method for forming trench-gate field effect transistor with source plug

A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.

Methods of making power semiconductor devices with thick bottom oxide layer

A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.

Method of forming trench-gate field effect transistors

A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.

Lateral drain MOSFET with improved clamping voltage control

A field effect transistor includes a body region of a first conductivity type in a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminating within the semiconductor region. A source region of the second conductivity type extends in the body region adjacent the gate trench. The source region and an interface between the body region and the semiconductor region define a channel region therebetween which extends along the gate trench sidewall. A channel enhancement region of the second conductivity type is formed adjacent the gate trench. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.

Trench-gate field effect transistor with channel enhancement region and methods of forming the same

A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.

Method for forming active and gate runner trenches

A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.

Structure and method of forming a topside contact to a backside terminal of a semiconductor device

A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.

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Murray, UT, United States of America

Bruce Douglas Marchant