Qualcomm Incorporated

Brigham Navaja

Hong Bok We

Aniket Patil

Kuiwon Kang

Marcus Hsu

Houssam Jomaa

Terence Cheung

Yuzhe Zhang

Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Hybrid package apparatus and method of fabricating

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

Package comprising a die and die side redistribution layers (RDL)

Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

Passive component embedded in an embedded trace substrate (ETS)

Disclosed is an apparatus and methods for making same. The apparatus includes a substrate, a set of electrical contacts disposed on the surface of the substrate, and an electromagnetic interference (EMI) shield pedestal structure, disposed between an outer periphery of the set of electrical contacts and an outer portion of the substrate.

Electromagnetic interference shielding for packages and modules

A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

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San Diego, CA, United States of America

Brigham Navaja