International Business Machines Corporation

Shinko Electric Industries Co., Ltd.

Brian W Quinlan

Charles Leon Arvin

Charles L Reynolds

Thomas Weiss

Brian Michael Erwin

Jean Audet

Mark William Kapfhammer

Krishna R Tunga

Brian Richard Sundlof

Steven Paul Ostrander

Bhupender Singh

Sylvain Pharand

Jon Alfred Casey

Thomas Anthony Wassick

Shidong Li

Anson Jay Call

Francesco Preda

Karen P McLaughlin

Daniel Mark Dreps

Kirk David Peterson

Christopher David Muzzy

Kamal Kumar Sikka

Krishna Gandhi Sachdev

Sushumna Iruvanti

Sungjun Chun

Edmund D Blackshear

Daniel George Berger

Tuhin Sinha

Junji Sato

Steve Ostrander

Franklin M Baez

Pascale Gagnon

Clement J Fortin

Jean Labonte

Kelly May Chioujones

Rui Wang

Stephanie Allard

David Edward Turnbull

Jean-Francois Bachand

Denis Blanchard

Keiichi Hirabayashi

Yoichi Miyazawa

Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Multicomponent module design and fabrication

An integrated circuit package includes a substrate, a flip chip die, and a capacitor. The flip chip die is attached to the substrate via die-to-substrate interconnects. The capacitor is attached to the flip chip die via capacitor-to-die interconnects so that the capacitor occupies a region between the flip chip die and the substrate. Such placement of the capacitor on a flip chip die has the advantage of reducing the distance between the capacitor and its core, thereby reducing unwanted line inductance and series resistance effects. Integrated circuit performance is thereby enhanced.

Direct attachment of capacitors to flip chip dies

A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

Thin film capacitors for core and adjacent build up layers

An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

Enlarged conductive pad structures for enhanced chip bond assembly yield

A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

Mitigating thermal-mechanical strain and warpage of an organic laminate substrate

Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

Flip chip packaging rework

A device including a substrate, an upper capacitor, and a lower capacitor is described. The upper capacitor is mounted on the substrate and includes an upper body and a pillar that extends from the upper body towards the substrate. The lower capacitor includes a lower body that is disposed both lateral to the pillar and at least in part between the upper body and the substrate. Each of the upper capacitor and the lower capacitor is a respective discrete circuit component. Such capacitor stacking configurations facilitate the placement of larger numbers of capacitors in close proximity to microprocessor cores in integrated circuit modules without the need to increase module size.

Stacked capacitors for use in integrated circuit modules and the like

A module including a first semiconductor device, a second semiconductor device, a bridge support structure and a base substrate. The semiconductor devices each having first bonding pads having a first solder joined with the base substrate and the semiconductor devices each having second and third bonding pads joined to second and third bonding pads on the bridge support structure by a second solder and a third solder, respectively, on the second and third bonding pads; the semiconductor devices positioned adjacent to each other such that the bridge support structure joins to both of the semiconductor devices by the second and third solders wherein the third bonding pads are larger than the second bonding pads and the third bonding pads are at a larger pitch than the second bonding pads.

Bridge support structure

A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.

Multiple chip carrier for bridge assembly

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Carrier and integrated memory

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.

An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

Connected plane stiffener within integrated circuit chip carrier

An IC device carrier includes organic substrate layers and wiring line layers therein. To reduce stain of the organic substrate layers and to provide decoupling capacitance, one or more decoupling capacitor stiffeners (DCS) are applied to the top side metallization (TSM) surface of the IC device carrier. The DCS(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the organic substrate layers, thereby mitigating the risk for cracks forming and expanding or other damage within the carrier. The DCS(s) also include two or more capacitor plates and provides capacitance to electrically decouple electrical subsystems of the system of which the DCS is apart.

Decoupling capacitor stiffener

A method includes affixing a capacitor sheet adjacent to core material of a device substrate, where the capacitor sheet covers a surface of the core material. The method also includes patterning first openings through both capacitor sheet and the core material, where the first openings are larger than a substrate pass through-hole. The method additionally includes filling the first openings with an electrically inert material. The method further includes patterning a second openings parallel to the first openings through the electrically inert material, where the second openings are at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.

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Poughkeepsie, NY, United States of America

Brian W Quinlan