Freescale Semiconductor,inc.

Motorola Corporation

Brian W Condie

Mahesh K Shah

Lakshminarayan Viswanathan

David James Dougherty

Richard W Wetz

Mario M Bokatius

L Mali Mahalingam

Peter H Aaen

Mali Mahalingam

An embodiment of a semiconductor device includes a supporting member, a semiconductor die mounted on a portion of the supporting member, a buffer region, and a plastic encapsulation. The buffer region covers a portion of the die, and includes a resin and filler particles packed within the resin. The filler particles have a mix of filler sizes and are tightly packed within the resin. The buffer region has a first dielectric constant and a first loss tangent. The plastic encapsulation encloses at least part of the supporting member and the die. The plastic encapsulation includes a plastic material of a second dielectric constant and a second loss tangent, where the second dielectric constant is larger than the first dielectric constant and the second loss tangent is larger than the first loss tangent.

Semiconductor device with a buffer region with tightly-packed filler particles

A wirebond array () comprising a plurality of signal wiresand a plurality of ground wires () interdigitated with and substantially parallel to the set of signal wires (). In one embodiment, each of the plurality of signal wires () and ground wires () is attached to a first semiconductor device () (e.g., a microwave power device). In another, each of the plurality of signal wires () is further attached to a package lead (). In one embodiment, each of the plurality of ground wires () is further attached to a ground connection region () substantially coplanar with the package lead (). Alternatively, each of the plurality of signal wires () is further attached to a second semiconductor device, wherein each of the plurality of ground wires () is further attached to the second semiconductor device.

Methods and apparatus for a reduced inductance wirebond array

A semiconductor structure () includes a substrate () having a surface () and also includes one or more semiconductor chips () located over the substrate surface. The semiconductor structure further includes an electrical isolator structure () located over the substrate surface, where the electrical isolator structure includes one or more electrical leads () and an organic-based element () molded to the electrical leads. The semiconductor structure also includes a solder element () coupling together the electrical isolator structure and the substrate surface.

Semiconductor structure and method of assembly

Structure and method are provided for plastic encapsulated semiconductor devices having reduced package cross-talk and loss. Semiconductor die are first coated with a buffer region having a lower dielectric constant &#x3b5; and/or lower loss tangent &#x3b4; than the plastic encapsulation. The encapsulation surrounds the buffer region providing a solid structure. The lower &#x3b5; buffer region reduces the stray capacitance and therefore the cross-talk between electrodes on or coupled to the die. The lower &#x3b4; buffer region reduces the parasitic loss in the encapsulation. Low &#x3b5; and/or &#x3b4; buffer regions can be achieved using low density organic and/or inorganic materials. Another way is to disperse hollow microspheres or other fillers in the buffer region. An optional sealing layer formed between the buffer region and the encapsulation can mitigate any buffer layer porosity. The buffer region desirably has &#x3b5; less than about 3.0 and/or &#x3b4; less than about 0.005.

Semiconductor device with reduced package cross-talk and loss

Structure and method are provided for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die are coated with the buffer layer. The buffer layer is patterned to expose the die bonding pads but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.

Plastic packaged device with die interface layer

A semiconductor structure () includes a substrate () having a first surface () with a mold lock feature (). The semiconductor structure also includes a semiconductor chip () located over the first surface of the substrate. The semiconductor structure further includes an electrical isolator structure () located over the first surface of the substrate. The electrical isolator structure includes an electrical lead () and an electrically insulative element () molded to the electrical lead. An optional portion () of the electrical isolator structure is located in the mold lock feature. The semiconductor structure additionally includes an adhesive element () located between and coupling the electrical isolator structure and the first surface of the substrate.

Semiconductor structure and method of manufacture

A method is provided for manufacturing a semiconductor device from a substrate () having an active surface () and a non-active surface (). The method comprises depositing a backing material () onto the non-active surface of the substrate () in a pattern (), the pattern () having at least a first die section (), a second die section () adjacent the first die section (), and a strip () connecting the first die section () and the second die section (), removing material from portions of the non-active surface of the substrate () on which the backing material () is not deposited to thereby partially separate the substrate () into a first die () and a second die () connected to one another by the strip () of the deposited backing material, and breaking the strip connector () to separate the first die () from the second die ().

Chemical die singulation technique

A semiconductor device () is provided which comprises a substrate and a die () having a first surface which is attached to the substrate by way of a die attach material. At least a portion () of the perimeter of the die is resistant to wetting by the die attach material, either through treatment with a dewetting agent or by selective removal of the backside metallization. It is found that this construction allows the surface area of the die to be increased without increasing the incidence of cracking and chipping along the sawn edges of the die.

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Mesa, AZ, United States of America

Brian W Condie